EP20K600CF672C9N - 600K Gate APEX 20KC FPGA | Intel | BGA-672
MPN: EP20K600CF672C9N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $255 | $2,550.00 |
| 100 | $220 | $22,000.00 |
| 500 | $195 | $97,500.00 |
| 1,000 | $175 | $175,000.00 |
EP20K600CF672C9N Overview
A Field-Programmable Gate Array (FPGA) is a reconfigurable semiconductor that lets engineers implement arbitrary digital logic via an SRAM or antifuse configuration bitstream. APEX 20KC sits within the broader taxonomy: FPGA -> programmable logic device (PLD) -> logic IC -> integrated circuit -> semiconductor. It supersedes the APEX 20KE family by integrating MultiCore architecture with embedded system blocks, and is targeted at ASIC-replacement and high-bandwidth glue-logic designs in telecommunications, video processing, and industrial control.
Key features include a 1.71 V to 1.89 V core supply (nominally 1.8 V), 250 MHz internal operating frequency, 1.48 ns pin-to-pin delay, fine-grain Look-Up Table (LUT) logic elements, dedicated carry chains, and a thermally enhanced FC-FBGA package. The device supports in-system reconfigurability through the IEEE 1149.1 JTAG interface, plus passive or active serial configuration modes, enabling remote firmware updates without powering down the host system.
The EP20K600CF672C9N integrates MultiCore blocks that combine LUT-based logic, embedded array blocks (EABs), and FastTrack interconnect, supporting up to 311,000 RAM bits. Its 672-pin FineLine BGA at 1.00 mm pitch allows dense board layouts, while the 0 to 85 C commercial temperature grade suits indoor and controlled-airflow chassis. Architecture is centered on SRAM-based configuration memory that must be loaded at every power-up, so designers typically pair the FPGA with a configuration PROM such as the EPC16 or EPC2.
Typical applications include high-speed telecom line cards, video broadcast encoders, industrial motor control, and ASIC prototyping. With 600K gates of logic capacity, the EP20K600CF672C9N is also deployed in test-and-measurement equipment and high-performance DSP front-ends where parallel datapath throughput matters more than raw clock frequency.
When designing with this part, ensure the 1.8 V core rail is monotonic at power-up; non-monotonic ramps can corrupt SRAM configuration. Decoupling requires 0.1 µF and 10 µF capacitors placed within 5 mm of each power pin, and the JTAG chain must include a series 33 ohm termination to dampen reflections on the TCK line.
This page synthesizes distributor pricing, drop-in APEX 20KC family alternatives, and practical JTAG/power-ramp design notes not aggregated in any single manufacturer datasheet.
Drop-in alternatives for EP20K600CF672C9N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600CF672C9N (same form factor and footprint) — differing in Operating Temperature, Process Technology, Package, Speed Grade, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600CF672C9
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$171 / Unit
View Datasheet →EP20K600CF672C8N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$108 / Unit
View Datasheet →EP20K600CF672C7N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$108 / Unit
View Datasheet →EP20K600CF672-3
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$99.5 / Unit
View Datasheet →EP20K600CB672C8N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$69 / Unit
View Datasheet →EP20K600CF672C9N Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Device Type | Loadable PLD / SRAM FPGA |
| System Gates | 600,000 |
| Logic Elements | 24,320 |
| Maximum Operating Frequency | 250 MHz |
| Propagation Delay | 1.48 ns (per logic element) |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) |
| User I/Os | 488 |
| Total Terminals | 672 |
| Package Type | FineLine BGA (FC-FBGA), 1.00 mm pitch, 45 x 45 mm |
| Process Technology | 0.15 µm all-layer copper |
| Operating Temperature | 0 C to 85 C (commercial) |
| Mounting Type | Surface Mount |
| Configuration Interface | JTAG (IEEE 1149.1), passive serial, active serial |
| Embedded Memory | MultiCore EABs supporting up to 311,000 RAM bits |
EP20K600CF672C9N fineline bga (fc-fbga), 1.00 mm pitch, 45 x 45 mm Pin Configuration Guide
Pin configuration for EP20K600CF672C9N (fineline bga (fc-fbga), 1.00 mm pitch, 45 x 45 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K600CF672C9N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K600CF672C9N is suitable for 6 applications: Telecom Line Card Processing, Video Broadcast Encoder, ASIC Prototyping Platform, Industrial Motor Control, Test and Measurement Backplane, High-Performance DSP Front-End.
Telecom Line Card Processing
The EP20K600CF672C9N fits telecom line card datapaths because its 600K system gates, 24,320 logic elements, and 488 user I/Os can implement multi-channel packet classification, traffic shaping, and 10G MAC framer glue logic in a single device. Its 250 MHz internal Fmax supports line-rate processing on STS-192/STM-64 backplanes, while the 672-ball FC-FBGA package provides the high pin count required for parallel 64-bit datapath buses. Designers typically pair it with a POS-PHY Level-4 PHY or a quad SFI-4.2 SERDES companion.
Recommended
Video Broadcast Encoder
The EP20K600CF672C9N's 24,320 logic elements and 311 kbit embedded memory support real-time HD-SDI video encoding pipelines, including discrete cosine transform, motion estimation, and entropy coding blocks. Its 488 I/O pins accommodate 10-bit parallel video buses at 148.5 MHz pixel clock with room for audio embedding and ancillary data paths. The 1.8 V core and 0 to 85 C commercial temperature range suit studio-grade chassis without active cooling, and the FC-FBGA package's 1.00 mm pitch supports dense multi-board chassis layouts.
Recommended
ASIC Prototyping Platform
The EP20K600CF672C9N delivers 600K gates of SRAM-based logic capacity, making it an ideal platform for ASIC prototyping where designers map RTL designs onto the FPGA for hardware verification before tape-out. Its fine-grain LUT architecture preserves synthesis timing fidelity versus the target ASIC, and the JTAG interface enables rapid bitstream reload cycles during iterative debug. The 672-ball FC-FBGA package with 488 user I/Os gives prototype boards ample stimulus/observation channels, and the 1.8 V core simplifies bench power design.
Recommended
Industrial Motor Control
The EP20K600CF672C9N handles multi-axis industrial servo and stepper control loops where its 250 MHz performance drives simultaneous FOC, space-vector PWM, and encoder interface logic for up to 6 axes. Its 488 user I/Os accept quadrature encoder inputs from multiple motors, while the SRAM-based configuration supports field firmware updates over JTAG or active serial. The commercial 0 to 85 C operating range and surface-mount FC-FBGA package fit sealed industrial enclosures with conduction cooling.
Recommended
Test and Measurement Backplane
The EP20K600CF672C9N's high logic density and 488 I/Os make it well suited for protocol-aware test equipment backplanes, implementing multi-lane BERT, pattern generator, and protocol decoder functions in a single FPGA. Its 1.48 ns propagation delay per logic element ensures deterministic timing margins for compliance test fixtures, while the 1.00 mm pitch BGA simplifies multi-board stack assembly. Designers use the JTAG port for boundary-scan and In-System Programmability to update test patterns without disassembling the chassis.
Recommended
High-Performance DSP Front-End
The EP20K600CF672C9N supports radar, sonar, and software-defined radio DSP front-ends where its 24,320 logic elements implement multi-tap FIR filters, FFT butterflies, and digital down-conversion in parallel. Its 250 MHz internal Fmax drives sample rates up to 200 MSPS on 16-bit datapaths, while the 488 user I/Os accept multiple ADC/DAC channels with margin for control and status. The SRAM configuration enables runtime reconfiguration for mode switching between radar pulse profiles or radio waveforms.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600CF672C9N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600CF672C9 | EP20K600CF672C8N | EP20K600CF672C7N | EP20K600CF672-3 | EP20K600CB672C8N |
|---|---|---|---|---|---|---|
| Package | 672-ball FC-FBGA | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same |
| Brand | Intel | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| System Gates | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 |
| Speed Grade | 9 (fastest) | 9 | 8 | 7 | 3 (industrial) | 8 |
| User I/Os | 488 | 488 | 488 | 488 | 488 | 488 |
| Internal Fmax | 250 MHz | 250 MHz | 200 MHz | 170 MHz | 230 MHz | 200 MHz |
| Operating Temperature | 0 C to 85 C (commercial) | 0 C to 85 C | 0 C to 85 C | 0 C to 85 C | -40 C to 85 C (industrial) | 0 C to 85 C |
| Configuration Interface | JTAG, passive serial, active serial | Same | Same | Same | Same | Same |
Key Differentiators
- Highest APEX 20KC speed grade (9) with 250 MHz Fmax (vs EP20K600CF672C8N)
- Industrial temperature range option in same package (vs EP20K600CF672-3)
- SRAM-configurable vs. once-only antifuse alternatives (vs EP20K600CF672C7N)
Design Notes
The 1.8 V VCCINT rail must rise monotonically within 1 ms to avoid SRAM configuration memory corruption. Estimated: at 250 MHz and typical 60% toggle rate, the EP20K600CF672C9N draws roughly 1.5 A from VCCINT and 0.4 A from VCCIO, so use a 3 A LDO or buck converter with at least 10 µF bulk + 0.1 µF decoupling within 5 mm of each power ball. Tie all unused VCCIO pins to the active I/O bank supply.
The 672-ball FC-FBGA at 1.00 mm pitch requires microvia or laser-drilled stacked-via PCB technology. Per Altera APEX 20KC layout guidelines, escape-route the inner balls on a 0.5 mm grid with via-in-pad if board area is constrained, and use a 6-8 layer stackup with dedicated ground planes beneath the BGA. Ground balls should be stitched with at least 8 vias each to a continuous ground plane.
Series-terminate each LVTTL/LVCMOS output to 33 ohm at the FPGA pin to dampen reflections on the 50 ohm microstrip traces. Estimated: at 250 MHz toggle, trace lengths above 50 mm require source termination. For DDR-style interfaces, place the resistor 5 mm from the FPGA ball, and use signal-length matching to within 1.5 mm across the byte lane.
Do not leave CONFIG_DONE floating - tie it to VCCIO through a 10 kohm pull-up so the FPGA signals completion of configuration. A floating CONFIG_DONE can prevent downstream devices from seeing a valid configuration. Also, JTAG TCK requires a 33 ohm series termination at the FPGA pin to dampen ringing on long daisy-chained scan paths.
Compliance Information
Compliance status not specified in verified web data; the APEX 20KC family predates many modern compliance declarations. RoHS status flagged as [DATA_NEEDED] in specs.
