EP20K600CF672C9 - 600K Gate APEX 20KC FPGA, 672-FBGA | Intel / Altera
MPN: EP20K600CF672C9 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $256.5 | $2,565.00 |
| 100 | $228 | $22,800.00 |
| 500 | $199.5 | $99,750.00 |
| 1,000 | $171 | $171,000.00 |
EP20K600CF672C9 Overview
An FPGA (Field Programmable Gate Array) is a programmable logic device (PLD) — a class of semiconductor IC whose logic function is defined by user configuration after manufacturing. Within the IC hierarchy, FPGAs sit below ASICs in fixed-function density and above simple CPLDs in capacity, and they belong to the broader programmable logic family that includes SPLDs, CPLDs, and FPGAs. APEX 20KC sits in the high-density segment of this hierarchy, intended for system-level integration of buses, memory interfaces, and datapath logic.
Key features include 508 maximum user I/O pins (488 in this BGA), 24,320 LEs, 311 Kbits of embedded memory, fast propagation delays around 1.48 ns, and configurable JTAG-based in-system programmability via the IEEE 1149.1 boundary-scan interface. The 672-pin FC-FBGA package supports the I/O-rich routing needed for high-bandwidth memory and parallel bus interfaces, while the commercial 0 °C to 85 °C operating range targets telecom, industrial, and test equipment applications.
The architecture combines a Lookup-Table (LUT) based logic fabric with distributed EAB memory blocks, enabling implementation of wide datapath functions, FIFOs, and on-chip bus controllers without external SRAM. Multi-voltage I/O banks support interfacing to 1.5 V, 1.8 V, 2.5 V, and 3.3 V devices, simplifying mixed-voltage system design.
Typical applications include high-speed parallel bus interfaces, telecom line cards, DSP co-processing engines, and prototyping platforms for ASIC emulation. The combination of high logic density, ample embedded RAM, and abundant I/O makes this device suitable for designs that previously required multiple smaller FPGAs.
When designing with this part, pay close attention to power sequencing — the 1.8 V core and I/O rails must follow the recommended ramp order in the datasheet to avoid latch-up. Because the device is in production legacy status, second-source qualification of the surrounding supply chain is recommended for long-lifecycle programs.
Drop-in alternatives for EP20K600CF672C9 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600CF672C9 (same form factor and footprint) — differing in Process Technology, Operating Temperature, Speed Grade, Package Type, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600CF672C9N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$175 / Unit
View Datasheet →EP20K600CF672C8
✅ Drop-In✓ In Stock
$322.4109 / Unit
View Datasheet →EP20K600CF672C7
✅ Drop-In✓ In Stock
$2267.89 / Unit
View Datasheet →EP20K600CF672C7ES
✅ Drop-In✓ In Stock
$360 / Unit
View Datasheet →EP20K600CF672-2
✅ Drop-In✓ In Stock
$680 / Unit
View Datasheet →EP20K600CF672C9 Maximum Ratings & Electrical Characteristics
| Device Family | APEX 20KC |
| Typical Gate Count | 600,000 gates |
| Logic Elements (LEs) | 24,320 |
| Maximum User I/O | 488 pins |
| Embedded Memory (EAB) | 311 Kbits |
| Propagation Delay | 1.48 ns |
| Maximum Internal Frequency | 250 MHz |
| Core Voltage | 1.8 V |
| Process Technology | 0.15 µm all-layer copper-metal |
| Package Type | 672-pin FC-FBGA |
| Package Dimensions | 45 x 45 mm, 1.27 mm pitch |
| Total Pin Count | 652 balls |
| Operating Temperature | 0 °C to +85 °C (commercial) |
| Configuration Interface | IEEE 1149.1 JTAG / passive serial / EPC configuration |
EP20K600CF672C9 45 x 45 mm, 1.27 mm pitch Pin Configuration Guide
Pin configuration for EP20K600CF672C9 (45 x 45 mm, 1.27 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K600CF672C9.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K600CF672C9 is suitable for 6 applications: Telecom Line Card Interface, ASIC Prototyping Platform, High-Speed Datapath / DSP Co-Processor, Industrial Control Backplane, Test & Measurement Instrumentation, Legacy System Refresh & Bridge Logic.
Telecom Line Card Interface
The EP20K600CF672C9 fits telecom line card designs because its 488 user I/Os support multi-standard backplane interfaces such as H.110 CT Bus, UTOPIA, and POS-PHY Level 3. The 24,320 LEs accommodate cell/packet processing logic, while the 311 Kbits of EAB RAM provide on-chip buffering for cell descriptors and routing tables. Operating at 250 MHz internal clock with multi-voltage I/O banks (1.5/1.8/2.5/3.3 V), the device connects directly to legacy 5 V-tolerant bus transceivers via level shifters. The 672-pin FC-FBGA package delivers the I/O density required for 32-bit parallel datapaths without requiring a companion bridge chip.
Recommended
ASIC Prototyping Platform
The EP20K600CF672C9 is well suited for ASIC prototyping because its 600K-gate capacity maps directly onto mid-complexity ASIC RTL. Engineers can use Quartus II to synthesize production ASIC code into APEX 20KC primitives, accelerating pre-silicon validation. The 488 I/Os allow real-time stimulus and observation of the design-under-test, while the IEEE 1149.1 JTAG interface enables in-system debugging with SignalTap-equivalent logic analyzers. The 1.8 V core minimizes dynamic power during long bring-up cycles, and the FC-FBGA package supports high-speed probing fixtures for logic analysis. For multi-FPGA ASIC prototypes, the 672-BGA mechanical outline standardizes with the Site MPN list family.
Recommended
High-Speed Datapath / DSP Co-Processor
The EP20K600CF672C9 serves as a DSP co-processor in imaging, video processing, and radar signal chains because its 24,320 LEs implement parallel multiply-accumulate pipelines at 250 MHz. The 311 Kbits of EAB memory hold coefficient tables and FIFO buffers used in FIR/IIR filter stages, eliminating external SRAM in many designs. The 672-FBGA package delivers 488 user I/Os for interfacing to multi-channel ADCs/DACs and external DDR memory controllers. The 0.15 µm all-layer copper process minimizes interconnect delay, critical for sustained sample rates above 100 MHz in pipelined datapaths.
Recommended
Industrial Control Backplane
The EP20K600CF672C9 supports industrial backplane controllers because of its commercial 0–85 °C temperature range, abundant I/O for parallel fieldbus interfaces, and 1.8 V core with multi-voltage bank support for legacy 5 V/3.3 V peripherals. Its 488 user I/Os aggregate multiple PROFIBUS, CAN, or RS-485 channels into a single FPGA, reducing BOM cost. The on-chip EAB memory provides deterministic buffering for industrial control loops. The 672-FBGA package fits on VME/CompactPCI backplane daughter cards, and the device's NRND status requires careful second-source qualification for long-lifecycle industrial programs.
Recommended
Test & Measurement Instrumentation
The EP20K600CF672C9 fits test and measurement instruments because its 488 I/Os and 250 MHz fabric enable parallel pattern generation, protocol decoding, and high-speed data capture. The 311 Kbits of EAB memory store capture buffers and pattern sequences on-chip, reducing external memory cost. Multi-voltage I/O banks connect directly to 1.5 V LVDS, 2.5 V TTL, and 3.3 V CMOS probe channels without level shifters. The 672-FBGA package supports the dense mixed-signal PCB layouts typical of oscilloscope and logic-analyzer front ends. The device's JTAG boundary-scan chain simplifies board-level ICT (in-circuit test) coverage on production assemblies.
Recommended
Legacy System Refresh & Bridge Logic
The EP20K600CF672C9 is commonly deployed as a bridge/glue-logic replacement when modernizing legacy equipment. Its 488 user I/Os and configurable I/O standards let engineers map between obsolete bus protocols and contemporary interfaces (PCI to local bus, VME to Ethernet, etc.) without a full board redesign. The 24,320 LEs are sufficient for state-machine and FIFO control logic, while EAB memory holds translation tables. The 672-FBGA footprint matches original legacy BOMs, simplifying drop-in PCB re-spins. Multi-voltage I/O support enables direct interfacing to 5 V peripherals through on-chip bus-hold circuitry, eliminating external pull-up resistors.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600CF672C9 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600CF672C9N | EP20K600CF672C8 | EP20K600CF672C7 | EP20K600CF672C7ES | EP20K600CF672-2 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-pin FC-FBGA (45x45mm) | 672-pin FC-FBGA - same | 672-pin FC-FBGA - same | 672-pin FC-FBGA - same | 672-pin FC-FBGA - same | 672-pin FC-FBGA - same |
| Speed Grade | C9 | C9 (extended marking) | C8 | C7 | C7 (ES) | -2 |
| Logic Elements | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 |
| Maximum User I/O | 488 | 488 | 488 | 488 | 488 | 488 |
| Embedded Memory (EAB) | 311 Kbits | 311 Kbits | 311 Kbits | 311 Kbits | 311 Kbits | 311 Kbits |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- High-density LUT + EAB fabric in APEX 20KC generation (vs EP20K400CF672C9)
- C9 speed bin for maximum Fmax in the APEX 20KC family (vs EP20K600CF672C8)
- 672-pin FC-FBGA exposes maximum I/O count (vs EP20K600CB652C9)
Design Notes
Estimated: the APEX 20KC core current at 250 MHz with all 24,320 LEs active can exceed 1.5 A at 1.8 V VCCINT. Decoupling must include at least six 0.1 µF X7R ceramic capacitors distributed around the FC-FBGA footprint plus two 47 µF bulk tantalum or polymer capacitors near the regulator. VCCIO banks should be decoupled independently with 0.1 µF + 10 µF per bank. Source: Altera AN 117 application note on APEX 20K power distribution.
The 672-pin FC-FBGA at 1.27 mm pitch requires a 4-6 layer PCB with microvia or via-in-pad construction for reliable assembly. Recommended stack-up: top + signal + GND + PWR + signal + bottom, with controlled-impedance routing for LVDS and clock signals. Per the Altera AN 114 layout guideline, all 488 user I/O balls must fan out within the first 5 mm of the package perimeter to keep stub lengths under 2 mm.
Common pitfalls include (1) configuring I/O banks to non-standard VCCIO voltages that violate absolute-max ratings, (2) omitting the nCONFIG or nSTATUS pull-up resistors required by the JTAG configuration controller, and (3) forgetting to connect all GND balls — FC-BGA packages need ALL GND balls soldered for thermal dissipation. Estimated junction-to-ambient thermal resistance is around 12 °C/W without airflow; at 1.5 W internal dissipation a 200 LFM airflow is recommended to keep Tj below 100 °C.
Compliance Information
RoHS and lead-free status not stated in current manufacturer documentation as of 2026-09-08; verify with distributor material declaration files. AEC-Q100 not applicable for commercial-grade FPGA. Conflict-minerals compliance follows Intel's published CMRT filings.
