Altera

EP20K600EFC33-2X - APEX-20KE 600K Gates 1.8V FPGA | Altera

MPN: EP20K600EFC33-2X ✗ End of Life

In Stock Ships in 1-3 business days

1.71 V to 1.89 V (1.8 V nominal) Vdss 1020-ball FC-FBGA (33 mm x 33 mm) Package 200 MHz Speed

From $815 USD / Unit

MOQ: 1 |

Price updated: 2026-09-07

Volume Pricing

Qty	Unit Price	Extended
1	$1007.66	$1,007.66
10	$970	$9,700.00
100	$905	$90,500.00
250	$860	$215,000.00
500	$815	$407,500.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EP20K600EFC33-2X Overview

The Altera (Intel) EP20K600EFC33-2X is a member of the APEX-20KE family of Field Programmable Gate Arrays (FPGAs) integrating 600K gates, 24320 logic elements (cells), and 311296 bits of embedded RAM in a single 1020-ball Fine-pitch BGA package. Operating from a 1.71V to 1.89V core supply with a 200 MHz internal performance grade and built on a 0.15 um all-layer copper-metal process, it targets System-on-a-Programmable-Chip (SOPC) applications where high logic density and on-chip memory are both required.

An FPGA (Field Programmable Gate Array) is a programmable logic device that combines configurable logic blocks, programmable interconnect, and dedicated memory/DSP blocks on a single silicon die. FPGAs sit in the broader hierarchy of programmable logic devices (PLDs), above simple PLDs (SPLDs) and complex PLDs (CPLDs), and below fixed-function ASICs. APEX-20KE devices specifically provide Look-Up Table (LUT)-based logic elements with embedded system blocks (ESBs) that can be configured as either dual-port RAM or FIFO buffers.

Key features include 588 maximum user I/O pins, 1020-ball FCBGA packaging at 33 mm x 33 mm with 1.27 mm pitch, an industrial 0C to 85C operating temperature range, and multi-voltage I/O support allowing the device to interface with 1.5V, 1.8V, 2.5V, 3.3V, and 5.0V buses. The EP20K600EFC33-2X is fabricated using a 0.15-micron all-layer copper process that delivers approximately 35% faster design performance than the original APEX 20K family, while maintaining software and pin compatibility.

The device architecture combines four Logic Array Blocks (LABs) per row, MegaLAB structures, and a hierarchical interconnect that enables predictable timing closure. Programmable Interconnect Array (PIA) signals route globally while FastTrack interconnect provides direct LAB-to-LAB routing, balancing flexibility and performance for high-utilization designs.

Typical applications include telecommunications line cards, digital signal processing pipelines, high-speed data buffering, network switching fabric bridging, and industrial control coprocessors. The 311296-bit embedded RAM is particularly valuable in packet processing and buffering subsystems where external SRAM would otherwise consume board space.

When designing with this device, verify Quartus II (or MAX+PLUS II for legacy support) configuration toolchain availability and ensure PCB thermal management accounts for the 33x33 mm package thermal mass. Multi-voltage I/O banks require separate VCCIO supplies for each interface voltage used.

This page synthesizes distributor pricing, drop-in APEX-20KE family alternatives, and practical design notes that complement the manufacturer datasheet with information gained from real-world sourcing data.

Drop-in alternatives for EP20K600EFC33-2X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP20K600EFC33-2X (same form factor and footprint) — differing in Operating Temperature, Process Technology, Package, Family, Speed Grade.

EP20K600EBC652-1X

Intel

Operating Temperature: 0 °C to 85 °C

Process Technology: 0.15 µm

Package: 652-BGA