Intel

EP20K60ETC144-3N - APEX-20KE FPGA 60K Gates 2560 Logic Elements 144-LQFP | Intel

MPN: EP20K60ETC144-3N ✗ End of Life

In Stock Ships in 1-3 business days

1.8 V Vdss 144-LQFP (LFQFP, gull-wing, square body) Package 160 MHz to 182 MHz Speed 32,768 bits Memory

From $92 USD / Unit

MOQ: 1 |

Price updated: 2026-09-07

Volume Pricing

Qty	Unit Price	Extended
1	$145	$145.00
10	$132.5	$1,325.00
100	$118	$11,800.00
500	$105	$52,500.00
1,000	$92	$92,000.00

ℹ️ All prices are in USD

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EP20K60ETC144-3N Overview

The Intel EP20K60ETC144-3N is a member of the APEX-20KE family of FPGAs, integrating 60,000 gates, 2,560 logic elements and 32,768 bits of embedded memory in a 144-pin LQFP package (TQFP form factor with gull-wing leads). It operates from a 1.8V core supply, supports up to 92 user I/O pins, and is fabricated on a 0.22 µm CMOS process that delivers an internal frequency of 160–182 MHz with a 1.72 ns propagation delay, making it suitable for mid-density glue-logic, bus-interface, and DSP-front-end designs.

A field-programmable gate array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that the designer programs after manufacture to implement arbitrary digital functions. APEX-20KE specifically introduced MultiCore™ architecture integrating look-up tables, product-term logic, and embedded system-on-a-programmable-chip (SOPC) blocks, which placed it within the broader taxonomy of programmable logic devices: PLD → CPLD/FPGA → SRAM-based FPGA → APEX-20KE. This hierarchy matters when designers compare it against later Cyclone, Stratix or competing Xilinx Spartan families.

Key features include 32,768 bits of embedded SRAM (ESB), 92 maximum user I/O, in-system programmability via IEEE 1149.1 JTAG, dedicated PLL-style clock networks (LVDSL/LVDS-style high-speed inputs available on selected banks), and a low-power 1.8V core. The device is offered in the commercial 0 °C to +85 °C temperature grade and uses a gull-wing surface-mount 144-LQFP (LFQFP code) with square body for standard SMT reflow.

Architecturally, the APEX-20KE family combines fast on-chip SRAM and product-term logic with high-speed interconnect, enabling designers to consolidate multiple CPLDs and discrete glue logic into a single device. The 2560 logic cells and 60K typical gate count put this part in the lower-mid-density tier of legacy Intel/Altera programmable logic, often used for bus bridges, custom peripherals, and pre-processing pipelines feeding a host processor.

Typical applications include telecom line-card interface logic, industrial control and instrumentation front ends, video pixel processing, military/aerospace retrofit boards where long-term Altera tooling is preserved, and legacy ASIC-replacement designs. The 144-LQFP footprint allows hand-rework and prototyping that smaller BGA packages cannot.

When designing with this FPGA, ensure the Quartus II (or MAX+PLUS II) toolchain version supports the APEX-20KE device family - newer Quartus releases have removed legacy device support. Plan power-rail decoupling for the 1.8V VCCINT and any 2.5V/3.3V VCCIO bank supplies per the APEX-20KE handbook.

This page synthesizes distributor inventory, pin-compatible APEX-20KE drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.

Drop-in alternatives for EP20K60ETC144-3N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP20K60ETC144-3N (same form factor and footprint) — differing in Operating Temperature, Package, Speed Grade, Family, Core Supply Voltage (VCCINT).

EP20K60EFC144-2XN

Altera

Speed Grade: -2 (per MPN suffix)

Family: APEX-20K (MultiCore Architecture)

Core Supply Voltage (VCCINT): 1.71 V to 1.89 V