EP2AGX125EF29C5G - Arria II GX FPGA, 118K LE | Intel | 780-FBGA
MPN: EP2AGX125EF29C5G β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1285 | $1,285.00 |
| 10 | $1245 | $12,450.00 |
| 100 | $1180 | $118,000.00 |
| 250 | $1135 | $283,750.00 |
| 500 | $1090 | $545,000.00 |
EP2AGX125EF29C5G Overview
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit that can be reconfigured by the customer after manufacture to implement arbitrary digital logic. FPGAs sit within the programmable logic hierarchy as: programmable logic -> programmable logic device (PLD) -> FPGA. Arria II GX devices belong to Intel's mid-range, transceiver-equipped family, positioned between low-cost Cyclone and high-end Stratix families, targeting applications that need both high-speed serial and DSP/parallel processing without the power envelope of a Stratix part.
Key features include 8 transceiver channels supporting PCI Express Gen1/Gen2 (x1, x4) and several serial RapidIO and Gigabit Ethernet configurations; 12 transceiver-side PLLs and 8 fractional PLLs on the core fabric; dedicated 18x18 multipliers supporting up to 590 GMACS DSP performance; 8.3 Mbits of M9K block RAM plus 1.5 Mbits of MLAB distributed memory; and up to 372 user I/O across 12 I/O banks supporting LVDS, DDR2/DDR3, LVTTL, LVCMOS, SSTL, and HSTL I/O standards.
The architecture combines a power-optimized logic fabric with hard IP blocks for transceivers, PCIe, and external memory interfaces, allowing deterministic timing closure for high-throughput signal-processing applications while keeping the part within a single 780-pin FC-FBGA outline (29 mm x 29 mm, 1.0 mm pitch). The transceiver hard IP blocks implement PCS and PMA layers in silicon, offloading serialization from user logic.
Typical applications include wireless baseband processing, military radar signal chains, video broadcast infrastructure, high-speed imaging, industrial test equipment, and PCIe-based coprocessor cards. The combination of transceivers, dedicated DSP blocks, and abundant block RAM makes it a strong fit for digital signal processing pipelines.
When designing with this device, the PCB must implement length-matched differential pairs for all transceiver channels (typically 6 layers or more) and a 12-layer stack-up is recommended for PCIe Gen2 compliance. Quartus II design software is required for place-and-route, and IBIS models are needed for signal-integrity simulation of the LVDS/DDR interfaces.
This page synthesizes distributor pricing, Arria II GX drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EP2AGX125EF29C5G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX125EF29C5G (same form factor and footprint) β differing in Package, Speed Grade, Operating Temperature, Family, Logic Elements.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGX125EF29C4G
β Drop-Inβ In Stock
$1100 / Unit
View Datasheet βEP2AGX125EF29C6G
β Drop-Inβ In Stock
$1495 / Unit
View Datasheet βEP2AGX125EF29C6N
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX125EF29I5N
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX125EF29C5N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2AGX125EF29I5G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$861.62 / Unit
View Datasheet βEP2AGX125EF29C5G Maximum Ratings & Electrical Characteristics
| Family | Arria II GX |
| Series | Arria II GX |
| Logic Elements (LE) | 118,143 |
| Adaptive Logic Modules (ALM) | 49,600 |
| Embedded Memory Bits | 8,315,904 |
| M9K Block RAM Blocks | 730 |
| MLAB Memory | 1,512 Kbits |
| 18x18 Multipliers | 590 |
| User I/Os | 372 |
| I/O Banks | 12 |
| Transceiver Channels | 8 |
| Transceiver Data Rate (max) | 3.75 Gbps |
| Process Technology | 40 nm |
| Core Voltage | 0.9 V |
| Speed Grade | C5 (commercial) |
| Package | 780-FBGA (FCBGA, 29x29 mm, 1.0 mm pitch) |
| Operating Temperature | 0C to +85C (commercial) |
| RoHS Status | Compliant |
| Mounting Type | Surface Mount |
EP2AGX125EF29C5G 780-fbga (fcbga, 29x29 mm, 1.0 mm pitch) Pin Configuration Guide
Pin configuration for EP2AGX125EF29C5G (780-fbga (fcbga, 29x29 mm, 1.0 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX125EF29C5G.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX125EF29C5G is suitable for 7 applications: Wireless Baseband Processing, Military Radar Signal Processing, Video Broadcast Infrastructure, High-Speed Imaging Systems, Industrial Test and Measurement Equipment, PCIe-Based Coprocessor Cards, Software Defined Radio Platforms.
Wireless Baseband Processing
The EP2AGX125EF29C5G's combination of 590 18x18 multipliers and 8.3 Mbits of block RAM delivers approximately 590 GMACS of DSP throughput, which is well-matched to WCDMA, LTE, and WiMAX baseband channel-card signal chains. The 8 transceiver channels at 3.75 Gbps support CPRI/OBSAI links to remote radio heads, while the 372 user I/Os allow multi-antenna MIMO aggregation with dedicated LVDS pairs for antenna data. The 40 nm low-power process keeps per-watt efficiency higher than older Stratix II GX designs, making it suitable for compact base-station line cards. Quartus II DSP Builder blocks accelerate FFT and channel-filter implementation.
Recommended
Military Radar Signal Processing
Radar front-end processing requires deterministic latency for pulse compression, moving-target indication (MTI), and beamforming - exactly the workload profile of the EP2AGX125EF29C5G. The 590 DSP blocks enable parallel FIR filter banks at hundreds of MHz, while 8.3 Mbits of block RAM holds complex range-bin samples in real time. The 8 transceivers digitize ADCs at up to 3.75 Gbps, eliminating external deserializer FPGAs. Designers typically pair the EP2AGX125 with high-speed ADCs such as the AD9268 over LVDS, then route aggregated data to a host processor. Conformal coating and vibration-tolerant PCB design are recommended for field deployment.
Recommended
Video Broadcast Infrastructure
Broadcast video routing and processing cards rely on the EP2AGX125EF29C5G's abundant I/O bandwidth and DSP blocks for SDI/HD-SDI/3G-SDI multiplexing, format conversion, and frame-rate conversion. The 372 user I/Os accept multiple SDI streams in parallel, while 8.3 Mbits of block RAM hold line and frame buffers needed for scaling and de-interlacing. The 8 transceivers support 3G-SDI (2.97 Gbps) and emerging 6G/12G-SDI via external muxing. PCIe Gen2 x4 hard IP enables direct host integration in server-based broadcast appliances. The Arria II GX price point offers better density than Cyclone V and lower power than Stratix IV GX for mid-density video workloads.
Recommended
High-Speed Imaging Systems
Industrial and scientific imaging systems stream multi-gigabit pixel data from CMOS sensors to processing pipelines - a workload suited to the EP2AGX125EF29C5G's 8 transceivers and 590 multipliers. Image preprocessing (white balance, demosaicing, defect correction) maps efficiently onto the DSP blocks, while block RAM stores line buffers for pipelined pixel processing. The 12 I/O banks support LVDS sensor interfaces with 372 user I/Os for parallel image sensors, while the transceivers connect to emerging MIPI-CSI and CoaXPress high-speed image links. The 40 nm process keeps thermal output manageable in enclosed camera housings.
Recommended
Industrial Test and Measurement Equipment
ATE (Automatic Test Equipment) and bench-top instrumentation leverage the EP2AGX125EF29C5G for pattern generation, waveform synthesis, and protocol decoding. The 8 transceivers capture multi-lane bus traffic (USB 3.0, PCIe, SATA, 10 GbE) directly into the FPGA for real-time protocol analysis. The 590 DSP blocks accelerate FFTs, FIR filters, and digital down-conversion used in vector signal analyzers and oscilloscopes. The 8.3 Mbits of block RAM hold deep acquisition memory, while 372 user I/Os drive front-panel displays and trigger inputs. JTAG-based bitstream loading simplifies factory test and field firmware updates.
Recommended
PCIe-Based Coprocessor Cards
The EP2AGX125EF29C5G's hard PCIe Gen2 IP blocks (x1 and x4 lanes) make it ideal for host-coprocessor acceleration cards in servers and workstations. The 118,143 logic elements provide abundant capacity for custom compute kernels, while 8.3 Mbits of block RAM and 590 DSP blocks accelerate compute-intensive algorithms. The 8 transceivers support PCIe Gen2 x4 (5 Gbps per lane) and additional sideband links to companion FPGAs or high-speed DACs/ADCs. Typical use cases include cryptographic acceleration, machine-learning inference, signal-processing pipelines, and storage controllers. The 780-FBGA F29 package supports standard PCIe card mechanicals.
Recommended
Software Defined Radio Platforms
Software Defined Radio (SDR) platforms for tactical, public-safety, and cellular infrastructure use the EP2AGX125EF29C5G's 8 transceivers and DSP blocks to implement wideband digital down-conversion, channelization, and modulation/demodulation. The 3.75 Gbps per channel supports multi-band RF aggregation, while 590 18x18 multipliers implement digital filtering at hundreds of MHz. The 8.3 Mbits of block RAM hold deep capture buffers for spectrum analysis, and the 372 user I/Os interface with companion RF front-end ICs. Nios II soft-core integration enables embedded control alongside the DSP pipeline.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX125EF29C5G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX125EF29C4G | EP2AGX125EF29C6G | EP2AGX125EF29C6N | EP2AGX125EF29I5N |
|---|---|---|---|---|---|
| Package | 780-FBGA (F29, 29x29 mm, 1.0 mm pitch) | 780-FBGA (F29) - same | 780-FBGA (F29) - same | 780-FBGA (F29) - same | 780-FBGA (F29) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Speed Grade | C5 (commercial) | C4 (faster) | C6 (slower) | C6 (slower) | I5 (industrial) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | -40C to +100C (industrial) | -40C to +100C (industrial) |
| Logic Elements | 118,143 | 118,143 | 118,143 | 118,143 | 118,143 |
| Embedded Memory | 8,315,904 bits | 8,315,904 bits | 8,315,904 bits | 8,315,904 bits | 8,315,904 bits |
| Transceiver Channels | 8 at up to 3.75 Gbps | 8 at up to 3.75 Gbps | 8 at up to 3.75 Gbps | 8 at up to 3.75 Gbps | 8 at up to 3.75 Gbps |
| User I/Os | 372 | 372 | 372 | 372 | 372 |
| Lifecycle Status | NRNR | NRNR | NRNR | NRNR | NRNR |
Key Differentiators
- C5 commercial speed grade balances performance and yield (vs EP2AGX125EF29C4G)
- Commercial temperature range optimized for cost (vs EP2AGX125EF29C6N)
- 8 transceivers in 780-FBGA footprint (vs EP2AGX125EF29I5N)
Design Notes
The EP2AGX125EF29C5G's 780-FBGA F29 package requires a minimum 8-layer PCB stack-up with controlled-impedance routing for all 8 transceiver channels. Differential pairs must be length-matched to within 5 mils (0.127 mm) per PCIe Gen2 compliance. Use 1.0 mm pitch BGA escape with via-in-pad or microvia technology to break out the inner balls. The PCB must provide solid ground planes on layers 2 and N-1 with stitched ground vias around all high-speed signal vias. Per the Arria II GX handbook, JTAG and configuration pins require 4.7 kohm pull-ups to VCCPD.
At typical workload, the EP2AGX125EF29C5G consumes approximately 8-12 W. Use a heatsink with thermal interface material or forced-air cooling to maintain junction temperature below 100C. The F29 FCBGA package has a junction-to-ambient thermal resistance (theta_JA) of approximately 12 C/W with appropriate PCB thermal vias and copper pours. Place 5x5 thermal via arrays under the package center BGA balls per the package thermal design guidelines. Without active cooling, derate maximum ambient operating temperature by 5C per 1 W of additional dissipation beyond typical.
The EP2AGX125EF29C5G requires four separate power rails: VCC (0.9 V core), VCCPD (3.3 V or 2.5 V I/O pre-driver), VCCIO (1.2 V to 3.3 V per bank), and VCCR/VCCT (1.1 V transceiver analog supply). Decoupling requires 100 nF ceramic caps within 100 mils of every power pin, plus bulk 220 uF tantalum or polymer capacitors on each rail. Power sequencing: VCC must ramp before VCCPD, and VCCIO must not exceed VCCPD by more than 0.7 V to avoid latch-up. Use TI TPS54xxx or LTM46xx modules with soft-start for hot-plug safety.
For LVDS signaling at the 372 user I/Os, target 100 ohm differential impedance with 50 ohm single-ended. Use IBIS models from Intel to simulate signal integrity before PCB fabrication. DDR2/DDR3 interfaces require matched-length byte lanes within 50 mils of each other; use fly-by topology with VTT termination at the far end. The transceiver reference clock input requires an ultra-low-jitter oscillator (less than 100 fs RMS jitter) to meet PCIe Gen2 jitter budgets. Avoid routing high-speed signals across power plane splits.
Common pitfalls: (1) Forgetting to connect all GND balls - unused BGA balls still need to be soldered and connected to the ground plane for thermal dissipation; (2) Using the wrong configuration mode - select MSEL pins for AS (active serial), PS (passive parallel), or JTAG configuration per design intent; (3) Inadequate configuration flash - Arria II GX configuration bitstreams can be 30-40 Mbits, requiring EPCS64 or larger flash; (4) Skipping CRC error injection test - run the built-in self-test to verify configuration memory integrity before production.
Compliance Information
RoHS and REACH compliant per Intel/Altera product declaration. Lead-free assembly per JEDEC J-STD-020. AEC-Q100 not applicable (commercial-grade FPGA). Halogen-free status not stated in verified data.
