EP2AGX190EF29C5G - Arria II GX FPGA, 190K LE, 780-FBGA | Altera
MPN: EP2AGX190EF29C5G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1786.66 | $1,786.66 |
| 10 | $1607.99 | $16,079.90 |
| 100 | $1429.33 | $142,933.00 |
| 500 | $1250.66 | $625,330.00 |
| 1,000 | $1071.99 | $1,071,990.00 |
EP2AGX190EF29C5G Overview
Background: An FPGA (Field-Programmable Gate Array) is a programmable logic device that allows designers to implement custom digital circuits after manufacturing. FPGAs sit within the broader taxonomy of programmable logic devices (PLDs) -> logic ICs -> integrated circuits -> semiconductors. Arria II GX family FPGAs specifically target mid-range applications requiring transceiver-based serial connectivity, such as broadband, wireless infrastructure, and broadcast equipment.
Key features include 372 user I/O pins, on-die termination (OCT), and a wide operating temperature range suited for industrial environments. The 'C5G' suffix denotes commercial temperature grade with -5 speed grade silicon. The device supports multiple I/O standards including LVDS, LVTTL, LVCMOS, and high-speed serial protocols.
Technical depth: The Arria II GX architecture employs adaptive logic modules (ALMs) instead of traditional 4-input LUTs, providing improved logic utilization. Hard memory controllers and DSP blocks accelerate common operations while reducing soft logic overhead. The transceiver blocks support multiple protocols including PCIe Gen2 x1/x4, XAUI, CEI-6.0, and Serial RapidIO.
Typical applications include wireless baseband processing, HD-SDI video processing, high-speed data acquisition, and PCIe Gen2 endpoint cards. When designing with this device, ensure proper power sequencing for the 0.9V, 1.1V, 1.5V, 2.5V, and 3.3V rails and adequate thermal dissipation via the exposed die. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design considerations sourced from DigiKey, Mouser, Octopart, and the Altera datasheet.
Drop-in alternatives for EP2AGX190EF29C5G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX190EF29C5G (same form factor and footprint) β differing in Package, Operating Temperature, Speed Grade, Family, Logic Elements.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGX190EF29C5N
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX190EF29C4G
β Drop-Inβ In Stock
$2510 / Unit
View Datasheet βEP2AGX190EF29C6G
β Drop-Inβ In Stock
$1010 / Unit
View Datasheet βEP2AGX190EF29I5N
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX190EF29I5G
β Drop-Inβ In Stock
$1900 / Unit
View Datasheet βEP2AGX190EF29I3G
β Drop-Inβ In Stock
$1195 / Unit
View Datasheet βEP2AGX190EF29C5G Maximum Ratings & Electrical Characteristics
| Series | Arria II GX |
| Number of Logic Elements | 181,165 |
| Number of CLBs | 7,612 |
| Total Memory Bits | 10,177,536 bits |
| Number of User I/O | 372 |
| Package | 780-BBGA, FCBGA (Flip Chip BGA) |
| Mounting Type | Surface Mount |
| Speed Grade | 5 (suffix C5G) |
| Temperature Grade | Commercial (C) |
| Process Technology | 40 nm |
| Transceiver Data Rate | Up to 6.375 Gbps |
| Hard Memory Controllers | Yes (DDR3, DDR2, QDR II+) |
| PCIe Hard IP | PCIe Gen2 |
| On-Die Termination (OCT) | Yes |
| RoHS Status | Compliant |
| MSL Level | 3 (per JEDEC J-STD-020) |
EP2AGX190EF29C5G 780-bbga, fcbga (flip chip bga) Pin Configuration Guide
Pin configuration for EP2AGX190EF29C5G (780-bbga, fcbga (flip chip bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX190EF29C5G.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX190EF29C5G is suitable for 6 applications: Wireless Baseband Processing, HD-SDI Video Processing, PCIe Gen2 Endpoint Card, High-Speed Data Acquisition, Industrial Test and Measurement, Software Defined Radio (SDR).
Wireless Baseband Processing
The EP2AGX190EF29C5G is well-suited for wireless baseband processing in 4G/LTE base station designs, where its 181,165 logic elements provide ample capacity for high-throughput channel decoding and protocol stack processing. The integrated 6.375 Gbps transceivers natively support CPRI and OBSAI backhaul interfaces common in remote radio head applications. With hard PCIe Gen2 endpoints, the FPGA also serves as an accelerator card for centralized baseband units. The 372 user I/Os allow direct connection to RF front-end ADCs/DACs and backplane interconnect, while DDR3 memory controller hard IP enables line-rate buffering of IQ sample streams.
Recommended
HD-SDI Video Processing
For HD-SDI broadcast and professional video applications, the EP2AGX190EF29C5G delivers the logic density required to handle multi-channel SD/HD/3G-SDI streams simultaneously. Its 372 user I/Os accommodate parallel video bus connections while high-speed transceivers drive SDI coaxial outputs at up to 6.375 Gbps, supporting 3G-SDI and 6G-SDI standards. On-chip memory of 10.18 Mbits provides frame buffering for video processing algorithms including scaling, color space conversion, and frame synchronization.
Recommended
PCIe Gen2 Endpoint Card
The EP2AGX190EF29C5G integrates PCI Express Gen2 hard IP blocks, making it ideal for endpoint accelerator cards in server and workstation applications. With up to 8-lane Gen2 support (5 Gbps per lane), the device delivers 4 GB/s aggregate bandwidth, suitable for high-speed data acquisition, protocol offload, or co-processing workloads. The 780-FBGA package provides robust thermal performance required for continuous high-bandwidth PCIe operation in server PCIe slots.
Recommended
High-Speed Data Acquisition
In high-speed data acquisition systems, the EP2AGX190EF29C5G serves as the central processing hub for digitizer and oscilloscope-class instruments. Its high-speed transceivers connect directly to ADC JESD204B/C serial outputs at multi-Gbps rates, while 372 I/Os support parallel LVDS interfaces to legacy ADCs. The 10.18 Mbit embedded memory supports real-time FFT buffers and trigger logic, and DDR3 controller hard IP enables deep capture memory expansion for long-duration recording.
Recommended
Industrial Test and Measurement
For industrial test and measurement equipment such as protocol analyzers and bit-error-rate testers, the EP2AGX190EF29C5G provides the logic capacity and transceiver bandwidth required for multi-channel BERT and protocol exerciser designs. Hard PCIe Gen2 endpoints enable direct host connection for high-throughput test data uploads, while flexible I/O banks support LVDS, LVCMOS, and HSTL standards required by mixed-signal instrumentation. The device's reliability makes it suitable for production-line test equipment.
Recommended
Software Defined Radio (SDR)
Software Defined Radio platforms benefit from the EP2AGX190EF29C5G's combination of high logic density and multi-gigabit transceivers, enabling wideband multi-channel radio designs. The integrated transceivers support ADC/DAC sampling rates from 100 MHz through 6.375 Gbps, accommodating most modern SDR architectures including LTE, 5G NR sub-6 GHz, and tactical military waveforms. Hard memory controllers enable efficient buffering of I/Q streams while the 7,612 CLBs provide ample DSP capacity for channelization and demodulation.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX190EF29C5G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX190EF29C5N | EP2AGX190EF29C4G | EP2AGX190EF29C6G | EP2AGX190EF29I5N |
|---|---|---|---|---|---|
| Package | 780-FBGA (F29) | 780-FBGA (F29) - same | 780-FBGA (F29) - same | 780-FBGA (F29) - same | 780-FBGA (F29) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Logic Elements | 181,165 | 181,165 | 181,165 | 181,165 | 181,165 |
| Speed Grade | -5 (C5G) | -5 | -4 (faster) | -6 (slower) | -5 |
| Temperature Grade | Commercial | Industrial | Commercial | Commercial | Industrial |
| Total Memory Bits | 10,177,536 | 10,177,536 | 10,177,536 | 10,177,536 | 10,177,536 |
| User I/O Count | 372 | 372 | 372 | 372 | 372 |
| Transceiver Data Rate | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps |
Key Differentiators
- Lowest temperature grade for cost-sensitive applications (vs EP2AGX190EF29C5N (industrial temp variant))
- Mid-range speed grade balances cost and performance (vs EP2AGX190EF29C4G (faster -4 speed grade))
- Integrated 6.375 Gbps transceivers eliminate external PHY cost (vs Cyclone V FPGAs without integrated transceivers)
Design Notes
The EP2AGX190EF29C5G requires multiple supply rails: 0.9V (VCC), 1.1V (VCCA_PLL), 1.5V/2.5V/3.3V (VCCIO banks). Per the manufacturer datasheet, power sequencing must follow VCCIO before or simultaneously with VCCA_PLL to prevent latchup. Use a dedicated sequencer IC such as the LM3880 and place bulk decoupling within 100 mils of each supply pin. Estimated total power at full utilization (all transceivers active, 50% toggle rate) is approximately 8-12W.
The 780-FBGA package requires thermal management via the exposed die on the bottom of the package. Per the manufacturer datasheet, the junction-to-ambient theta-JA is approximately 8-12 C/W depending on airflow and PCB thermal via count. Design the PCB with at least 16 thermal vias (0.3mm drill, 1mm pitch) under the package center to achieve rated performance. For high-utilization designs, a heatsink is recommended.
The 780-FBGA package has 1mm ball pitch, requiring 0.5mm PCB pads and microvia or sequential lamination PCB fabrication. Per IPC-7351 and JEDEC JESD51, use 4-6 layer stack-up with dedicated ground and power planes directly under the BGA. Differential pair length matching to within 5 mils for transceiver channels is required to maintain signal integrity at 6.375 Gbps.
Place the EP2AGX190EF29C5G such that transceiver channels route directly to board-edge SMA or high-speed connector without stubs. Per the manufacturer datasheet and AN530 (Altera transceiver layout guide), maintain 100 ohm differential impedance with no more than two vias per transceiver channel. Reference clock input should be routed as a 100 ohm differential pair with a guard ground on each side.
Do not confuse EP2AGX190 with EP2AGX190E - the 'E' suffix denotes enhanced hard IP blocks. Verify configuration mode pins are set correctly for AS (Active Serial), PS (Passive Serial), or JTAG. Per the manufacturer datasheet, MSL3 rating means floor life is 168 hours before bake-out is required. Always program the device's encryption key before deploying to production to prevent bitstream reverse engineering.
Compliance Information
RoHS compliant per distributor data. AEC-Q100 not applicable for FPGAs - this is not an automotive-qualified part. Verify halogen-free status with manufacturer datasheet if required.
