Intel

EP2AGX65CU17C6G - Arria II GX FPGA 65K LE | Intel | 6.375 Gbps

MPN: EP2AGX65CU17C6G ✓ Active

In Stock Ships in 1-3 business days

358-LFBGA / UBGA Package C6 Speed 5371904 Memory

From $141.28 USD / Unit

MOQ: 1 |

Price updated: 2026-09-08

Volume Pricing

Qty	Unit Price	Extended
1	$174.41	$174.41
10	$165.69	$1,656.90
100	$157.47	$15,747.00
500	$149.34	$74,670.00
1,000	$141.28	$141,280.00

ℹ️ All prices are in USD

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EP2AGX65CU17C6G Overview

The Intel (formerly Altera) EP2AGX65CU17C6G is a high-performance, low-power Arria II GX Field Programmable Gate Array (FPGA) with 60,214 logic elements, 5,371,904 bits of embedded memory, and 156 user I/Os, housed in a 358-pin LFBGA (UBGA) package. It integrates up to 6.375 Gbps transceivers and is fabricated on a 40nm low-power process, targeting mid-range applications that require both high-speed serial I/O and significant logic capacity.

An FPGA (Field Programmable Gate Array) is a reconfigurable integrated circuit that combines programmable logic blocks, interconnect, and I/O cells on a single die, belonging to the broader category of programmable logic devices (PLDs) within the digital semiconductor hierarchy: FPGA -> programmable logic -> logic IC -> integrated circuit -> semiconductor. FPGAs are widely used for digital signal processing, high-speed interface bridging, and ASIC prototyping. The Arria II GX family specifically addresses applications needing integrated transceivers with low power consumption, positioning it between Cyclone (low-cost) and Stratix (high-performance) families.

Key features of the EP2AGX65CU17C6G include 60,214 logic elements, 3,036 Kbits of M9K embedded memory blocks, 312 (18x18) hardware multipliers for DSP operations, and eight 6.375 Gbps transceiver channels. The device supports multiple I/O standards including LVDS, LVTTL, LVCMOS, and high-speed memory interfaces such as DDR3 SDRAM with dedicated PHY. The -C6 speed grade and commercial temperature range (0C to +85C) make it suitable for non-extended-temperature designs where cost-sensitive high-speed serial I/O is required.

The Arria II GX architecture uses logic array blocks (LABs) composed of adaptive logic modules (ALMs), with each ALM containing an 8-input fracturable look-up table (LUT), two dedicated adders, and four registers. The transceiver blocks embed clock data recovery (CDR), serializer/deserializer (SERDES), and word alignment circuitry, enabling protocols such as PCIe Gen1/Gen2, XAUI, Serial RapidIO, CPRI, and SDI without external PHY devices.

Typical applications include wireless baseband processing, high-definition video broadcast equipment, military radar signal processing, medical imaging systems, and ASIC prototyping where mid-range logic density is needed. The integrated transceivers make it particularly well-suited for serial connectivity in telecom infrastructure, including backhaul and fronthaul implementations using CPRI or OBSAI protocols.

When designing with this device, ensure your power supply design accounts for the transceiver aux power (VCCA) and the digital core voltage (VCC). Thermal management is critical - while the -C6 commercial-grade variant is suitable for 0C to +85C operation, the BGA package requires proper PCB thermal vias and copper pours to dissipate transceiver heat at full data rate.

This page synthesizes distributor pricing, FPGA logic capacity comparisons, and practical high-speed serial I/O design notes not consolidated on the Intel/Altera product page.

Drop-in alternatives for EP2AGX65CU17C6G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP2AGX65CU17C6G (same form factor and footprint) — differing in Package, Operating Temperature, Speed Grade, Process Technology, Transceivers.

EP2AGX65CU1713N

Altera

Package: 1713-ball FCBGA, 40 mm x 40 mm

Operating Temperature: 0C to +85C (commercial, suffix N)

Process Technology: 40 nm