EP2AGX95EF35C5G - Arria II GX FPGA, 89K LE, 1152-FBGA | Intel
MPN: EP2AGX95EF35C5G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $642.12 | $642.12 |
| 10 | $612.5 | $6,125.00 |
| 100 | $580 | $58,000.00 |
| 500 | $545 | $272,500.00 |
| 1,000 | $510 | $510,000.00 |
EP2AGX95EF35C5G Overview
An FPGA (Field-Programmable Gate Array) is a programmable logic device containing configurable logic blocks (CLBs), programmable interconnect, and dedicated hardware IP such as transceivers, DSP blocks, and memory controllers. Within the broader semiconductor taxonomy, an FPGA belongs to the programmable logic family, sitting between ASICs (fixed-function, high NRE) and microcontrollers (sequential processors); FPGAs deliver parallel hardware programmability for high-throughput signal processing, prototyping, and low-volume production. The Arria II GX family is positioned as Intel's mid-range transceiver-equipped FPGA for cost-sensitive applications requiring moderate logic density.
Key features include 8 transceivers operating up to 6.375 Gbps supporting protocols such as PCIe Gen2, Serial RapidIO, XAUI, and CEI-6G, 4 PCI Express hard IP blocks, 384 18x18 multipliers for DSP, and 4 hard memory controllers supporting DDR3, DDR2, and QDRII+. The 1152-pin FC-FBGA package supports high-speed serial lane routing and is rated for industrial-grade thermal operation.
Architecturally, the EP2AGX95EF35C5G uses a 40nm TSMC process, partial reconfiguration (PR) support, and adaptive logic modules (ALMs) that each contain two adaptive look-up tables (ALUTs). Hard IP blocks offload common functions like PCIe and memory interfaces, freeing fabric for application logic. The device supports both single-event upset (SEU) mitigation and zero-power static operation.
Typical applications include wireless baseband processing, radar and electronic-warfare front-ends, broadcast video processing, medical imaging accelerators, and industrial machine vision. Its transceiver density also suits protocol bridging, custom SerDes designs, and low-volume ASIC prototyping.
When designing with this device, careful signal-integrity planning is required for 6.375 Gbps lanes: use matched-length differential pairs, AC-coupling capacitors, and reference the Intel Arria II GX Transceiver User Guide for PCB stack-up. Power sequencing must follow the 0.9 V core / 1.1 V transceiver / 2.5 V-3.3 V I/O rail order documented in the device handbook.
This page synthesizes distributor pricing, drop-in same-brand alternatives from the Arria II GX family, and practical design considerations not consolidated in the manufacturer datasheet.
Drop-in alternatives for EP2AGX95EF35C5G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX95EF35C5G (same form factor and footprint) β differing in Package, Embedded Memory Bits, Package Type, Speed Grade, Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGX95EF35C4G
β Drop-Inβ In Stock
$1555 / Unit
View Datasheet βEP2AGX125EF35C5G
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Contact for price
View Datasheet βEP2AGX125EF35C4G
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$1290 / Unit
View Datasheet βEP2AGX95EF35C5G Maximum Ratings & Electrical Characteristics
| Series | Arria II GX |
| Family | Arria II GX |
| Logic Elements (LE) | 89,178 |
| Embedded Memory Bits | 6,839,296 bit |
| User I/O Pins | 452 |
| Number of LABs/CLBs | 3,747 |
| Supply Voltage (Core) | 0.9 V |
| Process Technology | 40 nm |
| Speed Grade | C5 |
| Package Type | 1152-BBGA, FCBGA (FineLine BGA) |
| Operating Temperature | 0C to +85C (Commercial) |
| Transceivers | Up to 8 (6.375 Gbps) |
| PCI Express Hard IP | Yes (Gen1/Gen2) |
| DSP Blocks (18x18 Multipliers) | Yes |
| Mounting Type | Surface Mount (BGA) |
EP2AGX95EF35C5G 1152-bbga, fcbga (fineline bga) Pin Configuration Guide
Pin configuration for EP2AGX95EF35C5G (1152-bbga, fcbga (fineline bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX95EF35C5G.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX95EF35C5G is suitable for 6 applications: Wireless Baseband Processing, Radar and Electronic Warfare Front-End, Broadcast Video Processing, Medical Imaging Accelerator, Industrial Machine Vision, ASIC Prototyping and Emulation.
Wireless Baseband Processing
The EP2AGX95EF35C5G suits wireless baseband processing with its 89,178 logic elements providing parallel DSP throughput for LTE and WiMAX PHY layer functions. Its 384 18x18 multipliers enable efficient FFT, channel estimation, and MIMO matrix operations, while the 8 multi-gigabit transceivers at 6.375 Gbps support CPRI/OBSAI fronthaul links to remote radio heads. The 6.839 Mbit embedded memory accommodates buffering of symbol-rate data without external SRAM, simplifying board layout and reducing BOM cost.
Recommended
Radar and Electronic Warfare Front-End
The EP2AGX95EF35C5G is well-matched to radar and electronic-warfare front-ends where high-speed ADC data must be processed in real time. The 8 transceivers at 6.375 Gbps accept digitized antenna signals from high-speed ADCs, while the 89,178 logic elements and 384 DSP multipliers implement pulse compression, MTI filtering, and digital beamforming in hardware. The -C5 speed grade supports the 500 MHz fabric clock rate required for sustained beamformer throughput under commercial temperature conditions.
Recommended
Broadcast Video Processing
The EP2AGX95EF35C5G addresses broadcast video processing requirements including 3G-SDI and HDMI bridging, format conversion, and on-screen display composition. Its 452 user I/Os accept multiple parallel video streams, while the embedded memory buffers full-HD frames for pipelined processing. The 4 PCI Express Gen2 hard IP blocks enable direct capture from PCIe-based video capture cards at 5 Gbps per lane. The 1152-ball FC-FBGA package supports the high pin density required for multi-stream video designs.
Recommended
Medical Imaging Accelerator
The EP2AGX95EF35C5G serves medical imaging systems including ultrasound beamformers, CT reconstruction pre-processors, and MRI gradient control. Its 384 18x18 multipliers accelerate the back-projection and Fourier-transform kernels central to image reconstruction, while the embedded memory holds temporary image slices without external DRAM access stalls. The device's deterministic low-latency transceivers synchronize with high-speed ADC front-ends, and the 452 user I/Os interface to image-display pipelines over LVDS or DisplayPort links.
Recommended
Industrial Machine Vision
The EP2AGX95EF35C5G enables high-throughput industrial machine vision with Camera Link, CoaXPress, or GigE Vision interface bridging. Its 8 multi-gigabit transceivers at 6.375 Gbps aggregate multiple high-speed image sensors, while 89,178 logic elements implement defect-detection algorithms and pre-processing filters in hardware. The 4 PCIe Gen2 hard IP blocks stream processed results to host CPUs at 5 Gbps per lane. Industrial temperature screening is not available for this commercial-grade part; for harsh environments, derate or select an industrial-grade Cyclone V/Arria V alternative.
Recommended
ASIC Prototyping and Emulation
The EP2AGX95EF35C5G is a popular platform for ASIC prototyping due to its 89,178 logic elements, abundant user I/Os, and high-speed transceivers that mimic ASIC pad-ring characteristics. Designers map ASIC RTL blocks into the FPGA fabric using Quartus II synthesis, then validate at near-ASIC clock rates before tape-out. The 1152-ball FC-FBGA package provides the high I/O count needed for SoC prototyping, and 4 PCIe Gen2 hard IP blocks allow co-simulation with host testbenches. Multiple EP2AGX95EF35C5G devices can be paralleled on a single prototyping board using the built-in transceivers for chip-to-chip bridging.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX95EF35C5G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX95EF35C4G | EP2AGX125EF35C5G | EP2AGX125EF35C4G |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 1152-BBGA, FC-FBGA (EF35) | 1152-BBGA, FC-FBGA (EF35) - same | 1152-BBGA, FC-FBGA (EF35) - same | 1152-BBGA, FC-FBGA (EF35) - same |
| Logic Elements | 89,178 | 89,178 (same) | 118,143 (+33%) | 118,143 (+33%) |
| Speed Grade | C5 | C4 (slower) | C5 (same) | C4 (slower) |
| Embedded Memory | 6,839,296 bit | 6,839,296 bit (same) | 8,294,400 bit (+21%) | 8,294,400 bit (+21%) |
| User I/O Pins | 452 | 452 (same) | 452 (same) | 452 (same) |
| Transceivers | Up to 8 (6.375 Gbps) | Up to 8 (6.375 Gbps) | Up to 12 (6.375 Gbps) | Up to 12 (6.375 Gbps) |
| PCIe Hard IP | 4 (Gen1/Gen2) | 4 (Gen1/Gen2) | 4 (Gen1/Gen2) | 4 (Gen1/Gen2) |
| Process / Core Voltage | 40 nm / 0.9 V | 40 nm / 0.9 V (same) | 40 nm / 0.9 V (same) | 40 nm / 0.9 V (same) |
Key Differentiators
- Highest pin count in the Arria II GX 95 sub-family (vs EP2AGX95DF25C5G)
- C5 speed grade delivers faster Fmax than C4 alternative (vs EP2AGX95EF35C4G)
- Lower unit cost than the higher-density 125 variant (vs EP2AGX125EF35C5G)
Design Notes
Estimated: The 1152-ball FC-FBGA package at 1.0 mm ball pitch requires a 4-6 layer PCB with 0.5 oz copper outer layers and 1 oz inner power/ground planes. Use a 1:1 via-in-pad microvia stack-up for breakout, with the BGA escape routed on the top layer within 0.5 mm of each pad. The exposed die-attach pad must be soldered to a thermal-via array (9+ vias per cm^2) tied to internal ground planes for proper heat extraction under full transceiver load.
The 6.375 Gbps transceivers require matched-length differential pairs with 100 ohm differential impedance, AC-coupling capacitors of 100 nF placed close to the receiver pins, and a continuous reference plane beneath the traces. The Intel Arria II GX Transceiver User Guide specifies the maximum lane-to-lane skew (under 1 UI) and recommends length-matching within 0.127 mm (5 mil). Use a 3D EM simulator (ANSYS HFSS, Cadence PowerSI) for the transceiver channel design, especially when routing through connectors or backplanes.
Estimated: The EP2AGX95EF35C5G draws up to 6-8 W under full transceiver utilization with all logic active, requiring a multi-rail supply (0.9 V core, 1.1 V transceiver PHY, 2.5 V/3.3 V I/O, 1.8 V auxiliary). Intel recommends a power-on sequencing order of 0.9 V first, then 1.1 V, then I/O rails, with monotonic ramp rates under 50 ms to avoid latch-up. Use a dedicated FPGA power-supply controller such as the Intel EN63A0QI or Texas Instruments TPS650250 to manage sequencing and voltage accuracy within +/-3%.
Common pitfalls with the EP2AGX95EF35C5G include: (1) forgetting to connect the exposed die-attach pad to ground, causing thermal runaway; (2) mis-assigning I/O bank voltages, leading to I/O bank failure during configuration; (3) using LVDS without external 100 ohm termination when the internal differential termination is disabled; (4) ignoring the JTAG chain configuration when multi-FPGA designs require TAP linking; (5) leaving unused transceiver channels floating instead of tying them to a quiescent state per Intel's guidelines.
Compliance Information
RoHS and REACH compliant per Intel/Altera Arria II GX product declaration. Lead-free (Pb-free) BGA balls compatible with 260C peak reflow per JEDEC J-STD-020. Halogen-free. Not AEC-Q100 qualified; for automotive applications, use Cyclone V or Arria V automotive-grade FPGAs. Conflict-mineral compliance statement available from Intel's CSR portal.
