EP2AGX95DF25C5G - Arria II GX FPGA, 89K LE, 6.8Mbit, 572-FCBGA | Intel
MPN: EP2AGX95DF25C5G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $968.85 | $968.85 |
| 10 | $921.2 | $9,212.00 |
| 100 | $875.4 | $87,540.00 |
| 500 | $818.55 | $409,275.00 |
| 1,000 | $768.9 | $768,900.00 |
EP2AGX95DF25C5G Overview
A Field-Programmable Gate Array (FPGA) is a semiconductor device built around a matrix of configurable logic blocks (CLBs), programmable interconnect, and embedded memory, DSP, and transceiver resources. FPGAs occupy the broad category hierarchy: FPGA -> programmable logic device (PLD) -> digital IC -> integrated circuit. Unlike fixed-function ASICs, FPGAs are reprogrammed in-system to implement custom digital logic, signal-processing pipelines, and high-speed serial protocols, making them ideal for low-volume designs, hardware prototyping, and systems whose feature set evolves after deployment.
Key features of the EP2AGX95DF25C5G include 8 integrated transceivers supporting data rates up to 3.75 Gbps, 8-input adaptive logic modules (ALMs) for fine-grained arithmetic, 8.5 x 9-bit multipliers configurable as 17 x 17 or 18 x 18 signed multipliers for DSP blocks, and dynamic phase-alignment circuitry for high-speed serial interfaces. The device supports LVDS, LVPECL, SSTL, HSTL I/O standards and offers 1.0 V core operation at the C5 speed grade.
Architecturally, the EP2AGX95DF25C5G uses a 40 nm process node, dedicated per-channel PMA blocks for each transceiver, and hardened PCI Express Gen1 hard IP. The C5 speed grade places it in the mid-range of Arria II GX device variants, balancing timing closure against power consumption for industrial and communications equipment.
Typical applications include wired telecommunications backplanes, industrial imaging pipelines, video broadcast equipment, ASIC prototyping, and PCI Express endpoint cards. The high I/O count and transceiver density make it especially well-suited to multi-channel serial-link aggregation designs.
When designing with this device, ensure the board layout supports the FCBGA 1.0 mm ball pitch with appropriate microvia stack-up, and use the Quartus II design suite (version 13.0 or later with Arria II device support) for synthesis, place-and-route, and timing closure.
Drop-in alternatives for EP2AGX95DF25C5G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX95DF25C5G (same form factor and footprint) — differing in Package, Operating Temperature, Speed Grade, DSP Blocks, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2AGX95DF25C4G
✅ Drop-In✓ In Stock
$360 / Unit
View Datasheet →EP2AGX95DF25C6G
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$290 / Unit
View Datasheet →EP2AGX95DF25I5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$636.37 / Unit
View Datasheet →EP2AGX65DF25C5G
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EP2AGX125DF25C5G
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$399.5 / Unit
View Datasheet →EP2AGX95DF25C5G Maximum Ratings & Electrical Characteristics
| Series | Arria II GX |
| Family | Arria II GX FPGA |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements (LE) | 89178 |
| Embedded Memory | 6839296 bit (6.8 Mbit) |
| Number of Logic Blocks / Cells | 6839296 memory bits, 89178 logic elements |
| User I/O Count | 260 |
| Number of Transceivers | 8 |
| Transceiver Data Rate | up to 3.75 Gbps |
| Package | 572-BGA, FCBGA (FineLine BGA) |
| Operating Temperature | 0C to +85C (commercial grade) |
| Speed Grade | C5 |
| Core Voltage | 1.0 V |
| Mounting Type | Surface Mount |
| Process Node | 40 nm |
| RoHS Status | Compliant |
EP2AGX95DF25C5G 572-bga, fcbga (fineline bga) Pin Configuration Guide
Pin configuration for EP2AGX95DF25C5G (572-bga, fcbga (fineline bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX95DF25C5G.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX95DF25C5G is suitable for 6 applications: Wired Telecommunications Backplane Aggregation, Industrial Imaging and Machine Vision Pipelines, PCI Express Endpoint Card Prototyping, Video Broadcast and Streaming Equipment, ASIC Prototyping and Emulation, Avionics and Defense Communications.
Wired Telecommunications Backplane Aggregation
The EP2AGX95DF25C5G is well-suited to multi-channel backplane aggregation designs in telecommunications equipment. Its 8 integrated transceivers support up to 3.75 Gbps per channel, giving an aggregate bandwidth of 30 Gbps that can be split across CPRI, OBSAI, Serial RapidIO, or proprietary backplane links. The 89,178 logic elements and 6.8 Mbit of embedded SRAM handle packet buffering, framer logic, and link-layer state machines without external memory for shallow queues. The 260 user I/O pins support parallel LVDS buses for legacy telecom fabrics. Designers can implement SONET/SDH mappers, Ethernet MACs, or proprietary serial protocols using the hardened PCS and PMA blocks. Unlike a discrete SERDES-plus-FPGA two-chip solution, the integrated transceivers reduce BOM cost and PCB area for 1U/2U line cards.
Recommended
Industrial Imaging and Machine Vision Pipelines
The EP2AGX95DF25C5G fits industrial machine-vision and broadcast imaging pipelines that require real-time Bayer demosaicing, color-space conversion, and HDR compositing. Its 8-input ALMs and dedicated 18x18 multipliers implement per-pixel DSP at CoaXPress, Camera Link, or GigE Vision input rates, while the 260 user I/Os absorb multiple parallel image sensor interfaces (LVDS sub-LVDS, HiSPi). The 6.8 Mbit embedded block memory holds several full-resolution scan lines for horizontal and vertical filtering kernels without external SRAM. Industrial-grade variants (I-temperature suffix) extend the operating range to -40C to +100C for factory-floor enclosures. The Arria II GX architecture, while older, retains mature reference designs for video bridging and remains a cost-effective choice for medium-volume vision systems where high-end Versal or Kintex UltraScale parts are overkill.
Recommended
PCI Express Endpoint Card Prototyping
The EP2AGX95DF25C5G integrates a hardened PCIe Gen1 hard IP block, making it a strong choice for PCI Express endpoint prototyping and low-volume production cards. The 8 transceivers support x1, x4, or x8 PCIe Gen1 lane configurations at 2.5 Gbps per lane, while the 89K logic elements implement the user-application logic, DMA engines, and protocol accelerators. The 6.8 Mbit embedded memory holds descriptor rings and small DMA buffers. The 572-FCBGA package supports enough I/O for high-bandwidth mezzanine connections such as FMC HPC, so evaluation kits exist (e.g., Altera/Intel Arria II GX PCIe dev kits). Engineers can shorten design cycles by reusing the PCIe reference design from the Quartus II IP catalog rather than licensing soft IP.
Recommended
Video Broadcast and Streaming Equipment
Broadcast video routers, frame synchronizers, and contribution encoders benefit from the EP2AGX95DF25C5G's mix of high-speed serial I/O, embedded memory, and parallel LVDS bandwidth. The 8 transceivers carry SDI (SMPTE 259M/292M/424M), DVB-ASI, or HDMI-over-Serial links, while 260 parallel I/Os interface to external video crosspoint switches, audio embedders, and AES/EBU serializers. The 6.8 Mbit embedded SRAM functions as line, frame, or GOP buffer memory for video format conversion (e.g., 1080i to 720p, 50 Hz to 59.94 Hz). The hardened PCS/PMA simplifies SMPTE-compliant clock recovery and cable equalization, removing an entire analog front-end IC. The C5 speed grade is adequate for SDI rates up to 3 Gbps and most broadcast frame-rate conversions in a single device.
Recommended
ASIC Prototyping and Emulation
The EP2AGX95DF25C5G serves as a cost-effective ASIC prototyping platform for medium-complexity ASICs up to ~10M gates. Its 89K LEs and 6.8 Mbit embedded memory model register-rich ASIC blocks, while the 8 transceivers replicate multi-gigabit SERDES I/O that target ASICs typically integrate. Designers can partition large ASIC designs across multiple Arria II GX devices using TDM or pin-multiplexing schemes; the 572-FCBGA DF25 package's known signal-integrity characteristics simplify multi-FPGA PCB design. The mature Quartus II synthesis flow supports ASIC-style Verilog/VHDL with timing-annotated SDF for bring-up correlation against the ASIC RTL. The Arria II GX family is widely deployed in commercial emulation boards and remains a workhorse for pre-silicon software development.
Recommended
Avionics and Defense Communications
Defense communications systems use the EP2AGX95DF25C5G for secure radio front-ends, MIL-STD-1553/ARINC-429 bridges, and tactical data link terminals where reliability and wide operating-temperature support are required. Industrial-grade (-40C to +100C) variants of the EP2AGX95DF25I5N handle cockpit and ground-mobile temperature swings. The 8 hardened transceivers carry Link-16, MADL, or proprietary waveforms at data rates from a few hundred Mbps to 3.75 Gbps, while 260 user I/Os interface to RF DACs/ADCs and discrete RF front-end components. The 6.8 Mbit embedded memory supports short-term buffering of packetized RF data. The mature Quartus II design flow with extensive DO-254 evidence is a major advantage for avionics certification cycles where newer FPGAs lack flight-history data.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX95DF25C5G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX95DF25C4G | EP2AGX95DF25C6G | EP2AGX95DF25I5N | EP2AGX65DF25C5G | EP2AGX125DF25C5G |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 572-BGA, FCBGA (DF25) | 572-BGA, FCBGA (DF25) | 572-BGA, FCBGA (DF25) | 572-BGA, FCBGA (DF25) | 572-BGA, FCBGA (DF25) | 572-BGA, FCBGA (DF25) |
| Logic Elements | 89178 | 89178 | 89178 | 89178 | 60214 | 124100 |
| Embedded Memory | 6.8 Mbit | 6.8 Mbit | 6.8 Mbit | 6.8 Mbit | 4.5 Mbit | 8.2 Mbit |
| User I/O | 260 | 260 | 260 | 260 | 414 | 260 |
| Transceivers | 8 (up to 3.75 Gbps) | 8 (up to 3.75 Gbps) | 8 (up to 3.75 Gbps) | 8 (up to 3.75 Gbps) | 8 (up to 3.75 Gbps) | 12 (up to 3.75 Gbps) |
| Speed Grade | C5 | C4 (faster) | C6 (slower) | I5 (industrial temp) | C5 | C5 |
| Operating Temperature | 0C to +85C | 0C to +85C | 0C to +85C | -40C to +100C | 0C to +85C | 0C to +85C |
Key Differentiators
- Balanced logic-memory-transceiver density for mid-complexity telecom designs (vs EP2AGX65DF25C5G)
- Mature Quartus II design flow with extensive IP and reference design ecosystem (vs EP2AGX260FF35C6G)
- Industrial temperature grade available in same package for harsh-environment variants (vs EP2AGX95EF29I5G)
Design Notes
The 572-FCBGA DF25 package uses a 1.0 mm ball pitch, which requires microvia PCB technology (laser-drilled blind/buried vias) for breakout routing. Use a stack-up with at least 4-6 layers and matched 50 ohm single-ended or 100 ohm differential trace impedance for the transceiver channels. Place decoupling capacitors on the power pads directly under the BGA using via-in-pad to minimize inductance.
Estimated: at the maximum transceiver utilization (8 channels at 3.75 Gbps) plus full DSP block utilization, the EP2AGX95DF25C5G can dissipate 8-12 W. The FCBGA package has a theta-JA of approximately 12 C/W with the recommended thermal via array and a heatsink. Engineers should attach a heatsink or thermal pad to the top of the package, plus provide forced-air cooling in 1U chassis designs to keep the junction below 100 C.
Each transceiver pair (P/N) should be routed as a length-matched differential pair with 100 ohm differential impedance, kept under 15 cm total length, and isolated from switching power supply traces by at least 3W spacing. AC-coupling capacitors (typically 100 nF X7R 0402) must be placed in series with each transmit output and receive input, with the capacitor pad impedance matching the trace. Reference the Arria II GX board design guidelines for full channel simulation methodology.
Do not assume the Arria II GX tool flow continues to receive updates; Quartus II versions 13.0sp1 or 13.1 are the last versions with full Arria II GX support, and Intel only ships maintenance patches. Validate that any IP cores (PCIe, DDR controller, transceivers) used in the design are still compatible with the Quartus II version you target. For new designs, prefer Cyclone V GX or Cyclone 10 GX with active Quartus Prime support.
Compliance Information
RoHS and REACH compliance stated by authorized distributors (DigiKey, Mouser). AEC-Q100 not applicable to FPGAs in standard automotive qualification; industrial-grade variants handle -40C to +100C but are not AEC-Q100 qualified.
