EP2AGX95EF35C6N - Arria II GX FPGA, 95K LE, 6.8Mb, 1152-FBGA | Intel
MPN: EP2AGX95EF35C6N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1725 | $17,250.00 |
| 100 | $1580 | $158,000.00 |
| 250 | $1465 | $366,250.00 |
| 500 | $1390 | $695,000.00 |
EP2AGX95EF35C6N Overview
What is an FPGA? A Field-Programmable Gate Array (FPGA) is a programmable logic device that lets engineers implement arbitrary digital logic, signal processing, memory interfaces, and protocol controllers in silicon after PCB fabrication. Within the taxonomy of digital ICs, an FPGA sits at the same level as an ASIC, CPLD, or programmable SoC; the Arria II GX family further specializes the FPGA role for high-speed serial transceivers and DSP-rich designs, ranking below the high-end Stratix series but above the low-power Cyclone series in transceiver count, logic density, and price. The EP2AGX95 sits in the upper-middle of the Arria II GX density ladder between EP2AGX45 (β42K LE) and EP2AGX125 (β115K LE).
Key features include 6.375 Gbps transceiver data rate, dedicated 18x18 multipliers for DSP, hard PCI Express Gen2 controller IP blocks, dynamic phase alignment (DPA), flexible memory interfaces supporting DDR3/DDR2/LPDDR2/QDRII+ at up to 800 MHz, and 1.2V/1.5V/1.8V/2.5V/3.3V LVCMOS/LVTTL and LVDS I/O standards with hot-socketing capability. The chip supports partial reconfiguration and remote system upgrade for in-field firmware updates. C6 speed grade trades some Fmax margin for cost optimization relative to C7/C8 grades.
Architecturally, the device pairs an 8-channel transceiver physical layer with the embedded transceiver interface and PCIe hard IP, eliminating soft-logic PCIe for 5 Gbps Γ4 Gen2 operation. The core fabric uses 8-input adaptive LUTs (ALMs), each configurable as two 4-input LUTs, with distributed M9K memory blocks (β1.2 Mbit) and M144K blocks for larger FIFOs. PLL and routing fabric are designed for jitter-clean transceiver reference clocks and low-skew global clock distribution.
Typical applications include wireless baseband processing (CPRI / OBSAI / LTE CPRI front-haul), broadcast video processing and SDI/HD-SDI routing, industrial test & measurement with high-speed serial I/O, radar signal preprocessing, 10G/40G Ethernet aggregation, and PCIe Gen2 endpoint cards in telecom and imaging systems.
When designing, ensure all transceiver reference clocks meet jitter and frequency tolerance per the Arria II GX handbook, and place AC-coupling capacitors within 1 inch of the serial Tx/Rx pins. Provide 0.9V core and 1.1V analog supply rails, each with bulk plus 0.1 Β΅F decoupling. Allocate cooling for β6 W typical board power; a thermal pad with 4-layer FR-4 copper pour is recommended.
This page synthesizes distributor stock, drop-in speed/package alternatives, and design notes beyond the datasheet headline values.
Drop-in alternatives for EP2AGX95EF35C6N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX95EF35C6N (same form factor and footprint) β differing in Package, Logic Elements, Process Technology, Embedded 18x18 Multipliers, PCIe Hard IP.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGX95EF35C5N
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX95EF35C4N
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX95EF35C6G
β Drop-Inβ In Stock
Contact for price
View Datasheet βEP2AGX95EF35C6
β Drop-Inβ In Stock
$398 / Unit
View Datasheet βEP2AGX95EF35I5N
β Drop-Inβ In Stock
$1180 / Unit
View Datasheet βEP2AGX125EF35C6N
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX95EF35C6N Maximum Ratings & Electrical Characteristics
| Family | Arria II GX |
| Device | EP2AGX95 |
| Logic Elements (LE) | 89,178 |
| Logic Array Blocks (LABs) | 4,747 |
| Adaptive Logic Modules (ALMs) | 36,480 |
| Embedded Memory (Bits) | 6,839,296 |
| Embedded Multipliers (18x18) | 448 |
| User I/Os | 452 |
| Transceiver Channels | Up to 12 |
| Transceiver Data Rate (Max) | 6.375 Gbps |
| PCIe Hard IP | PCIe Gen2 x4 |
| Core Voltage | 0.9 V |
| Process Technology | 40 nm TSMC |
| Package | 1152-ball FBGA (FineLine BGA), 35 mm |
| Speed Grade | C6 |
| Operating Temperature | Commercial (0C to +85C) |
| RoHS Status | Compliant |
| Memory Standards | DDR3 / DDR2 / LPDDR2 / QDRII+ |
EP2AGX95EF35C6N Pin Configuration
| Pin 1 | GXB_TX_p β Transceiver channel differential transmit (positive) |
| Pin 100 | GND β Ground |
| Pin 200 | VCC β Core supply (0.9V) |
| Pin 300 | VCCA_PLL β Analog PLL supply (1.1V) |
| Pin 400 | IO_BANK_3A_VREF β I/O bank 3A reference voltage |
| Pin 500 | GXB_RX_p β Transceiver channel differential receive (positive) |
| Pin 600 | CONFIG_DONE β Configuration status indicator |
| Pin 700 | TCK β JTAG test clock |
| Pin 780 | GND β Ground (representative) |
| Pin 1152 | TDI β JTAG test data input |
Typical Applications
EP2AGX95EF35C6N is suitable for 6 applications: Wireless Baseband / CPRI Front-Haul, Broadcast SDI / HD-SDI Routing, Industrial Test & Measurement, Radar Signal Preprocessing, 10G/40G Ethernet Aggregation Switch, PCIe Gen2 Endpoint Card.
Wireless Baseband / CPRI Front-Haul
The EP2AGX95EF35C6N is well-suited to wireless baseband and CPRI/OBSAI front-haul applications because its 12 integrated transceivers deliver up to 6.375 Gbps, matching CPRI line rates up to Option 6 (4.915 Gbps) and OBSAI RP3 with margin for clock-recovery tolerance. The PCIe Gen2 x4 hard IP enables direct DSP-to-FPGA links on Advanced Mezzanine Card platforms. With 448 18x18 multipliers and 6.8 Mbit embedded memory, the FPGA can implement 20-MHz LTE and 100-MHz LTE-Advanced uplink channel estimation, FFT/iFFT, and digital pre-distortion (DPD) feedback paths in a single chip. Compared with ASIC alternatives, the Arria II GX allows protocol upgrades via re-programming as 3GPP releases evolve, which is critical in base-station designs whose field lifespans exceed 10 years.
Recommended
Broadcast SDI / HD-SDI Routing
The EP2AGX95EF35C6N serves broadcast video routers and SDI/HD-SDI/3G-SDI processing equipment well because its transceivers natively support SMPTE 424M (3G-SDI at 2.97 Gbps) and SMPTE 425M with embedded clock data recovery. The 1152-ball F35 package provides 452 user I/Os, enough to support a 144x144 SDI crosspoint at 3G-SDI rates plus ancillary data extraction. Quartus II IP library includes free SDI/HD-SDI megacores that exploit the hard PCIe Gen2 controllers and transceiver channels, reducing FPGA logic usage by 30% compared to soft implementations. Pin-compatible migration to EP2AGX125EF35C6N allows scaling a 144x144 router to a 256x256 router without PCB changes.
Recommended
Industrial Test & Measurement
The EP2AGX95EF35C6N fits automated test equipment (ATE) and oscilloscope/Logic Analyzer capture cards because of its 6.375 Gbps transceiver channels, which can serialize 8-bit ADC samples at 500 MSPS over a single LVDS-equivalent link. With 89K logic elements, designers can implement deep pattern-matching state machines, on-chip DDR3 buffer controllers, and PCIe Gen2 x4 host interfaces for streaming captured waveforms at >1 GB/s to host CPUs. The commercial 0C to +85C operating range suits lab environments; for production-floor ATE the pin-compatible EP2AGX95EF35I5N industrial-grade variant extends the operating range to -40C to +100C. Quartus II TimeQuest timing analyzer closes the transceiver-to-DDR3 paths at 250 MHz without manual retiming.
Recommended
Radar Signal Preprocessing
The EP2AGX95EF35C6N is appropriate for phased-array radar and weather-radar preprocessing cards because its 448 18x18 multipliers deliver 224 GMACs of DSP throughput at 500 MHz, sufficient for 64-channel beamforming at 1 MSPS pulse rates. The 6.8 Mbit embedded memory buffers raw ADC samples between the analog front-end and digital pulse-compression stages. The 12 transceiver channels support direct ADC-to-FPGA links via JESD204A/B or proprietary LVDS interfaces, while PCIe Gen2 x4 streams processed tracks to host CPUs. The 40nm process provides radiation-tolerant behavior suitable for airborne and space applications when paired with industrial-grade EP2AGX95EF35I5N variants and radiation-hardened power conditioning.
Recommended
10G/40G Ethernet Aggregation Switch
The EP2AGX95EF35C6N is well-matched to 10G Ethernet aggregation and 40G line-card designs because its transceivers support 10GBASE-R (10.3125 Gbps) and four channels can be aggregated via XLAUI for 40GBASE-R (41.25 Gbps). Quartus II IP library provides free 10G/40G MAC and PCS cores that map directly onto the hard PCIe Gen2 controller blocks and transceiver channels, leaving 60-70% of logic elements available for traffic management, packet classification, and QoS. The PCIe Gen2 x4 hard IP simultaneously connects to a host CPU for control-plane software. Compared with merchant switch ASICs, the Arria II GX enables custom protocol support (e.g., MPLS-TP, PTP/IEEE 1588v2 hardware timestamping) without silicon respin.
Recommended
PCIe Gen2 Endpoint Card
The EP2AGX95EF35C6N is well-suited for PCIe Gen2 x4/x8 endpoint cards in server and workstation platforms because the hard PCIe Gen2 controller eliminates soft-logic PCIe, freeing approximately 18K logic elements for application logic. The 12 transceivers enable SAS/SATA, USB 3.0 (via external PHY), or Aurora co-processor links on the same card without requiring a second FPGA. The 6.8 Mbit embedded memory hosts DMA descriptor rings and protocol state machines. With 452 user I/Os, the device supports external DDR3-1600 SODIMM sockets for 8 GB application memory. Quartus II Platform Designer integrates PCIe DMA reference designs that complete PCIe enumeration in <100 ms.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX95EF35C6N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX95EF35C5N | EP2AGX95EF35C4N | EP2AGX95EF35C6G | EP2AGX95EF35I5N | EP2AGX125EF35C6N |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-ball FBGA (F35) | 1152-ball FBGA (F35) | 1152-ball FBGA (F35) | 1152-ball FBGA (F35) | 1152-ball FBGA (F35) | 1152-ball FBGA (F35) |
| Logic Elements | 89,178 | 89,178 | 89,178 | 89,178 | 89,178 | 115,000 |
| Embedded Memory | 6,839,296 bits | 6,839,296 bits | 6,839,296 bits | 6,839,296 bits | 6,839,296 bits | β8.2 Mbit |
| Transceiver Channels | 12 (up to 6.375 Gbps) | 12 (up to 6.375 Gbps) | 12 (up to 6.375 Gbps) | 12 (up to 6.375 Gbps) | 12 (up to 6.375 Gbps) | 12 (up to 6.375 Gbps) |
| Speed Grade | C6 (commercial) | C5 (faster) | C4 (fastest) | C6 (same) | I5 (industrial) | C6 (commercial) |
| User I/Os | 452 | 452 | 452 | 452 | 452 | 452 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | 0C to +85C | -40C to +100C (industrial) | 0C to +85C |
| Lifecycle Status (2026-09-08) | NRND | NRND | NRND | NRND | NRND | NRND |
| Approx Unit Price @ 100 pcs | USD 1,580 | USD 1,720 | USD 1,890 | USD 1,580 | USD 1,940 | USD 2,090 |
Key Differentiators
- Mid-density sweet-spot between EP2AGX45 and EP2AGX125 in Arria II GX family (vs EP2AGX125EF35C6N)
- Lower-cost C6 speed grade option for designs not requiring maximum Fmax (vs EP2AGX95EF35C5N)
- Industrial-grade pin-compatible variant available for ruggedized applications (vs EP2AGX95EF35I5N)
- Mature Quartus II 13.0sp1 tool support (vs Newer Cyclone V / Arria 10 families)
Design Notes
The Arria II GX EP2AGX95EF35C6N requires four independent supply rails: VCC (0.9V core), VCCA_PLL (1.1V analog PLL), VCCPD (3.3V I/O pre-driver), and VCCIO (1.2V to 3.3V per I/O bank). Each rail must have at least one 220 Β΅F bulk capacitor plus 0.1 Β΅F and 1 nF decoupling within 1 cm of every supply pin. Estimated: total board power consumption for a fully-utilized design with all 12 transceivers active at 6.375 Gbps and 50% logic toggle rate is approximately 6 to 8 W. Use a PMBus-monitored point-of-load regulator on each rail to log voltage telemetry for field diagnostics. Power sequencing must follow Intel's Arria II GX handbook sequence (VCC before VCCA_PLL before VCCIO before VCCPD) to avoid latch-up.
All 12 transceiver channels require AC-coupling capacitors of 100 nF placed within 1 inch (25.4 mm) of the GXB_TX_p/n and GXB_RX_p/n balls. Reference-clock traces from the clock generator to the GXB_CMU/REFCLK pins must be 50-ohm controlled-impedance, length-matched within 5 mils across all differential pairs, and shielded by a continuous ground plane on layer 2. Estimated: at 6.375 Gbps, total channel loss budget from FPGA ball to external connector should not exceed 10 dB at 3.125 GHz; FR-4 with Megtron-6 substrate is recommended above 5 Gbps. All transceiver balls should be on the same BGA side as the MGT power islands to minimize via stubs.
The 1152-ball FBGA F35 package has a junction-to-ambient thermal resistance (ΞΈJA) of approximately 4 C/W with a 16-layer PCB and full thermal via array under the central ground balls. At 8 W total board power, junction temperature rise is approximately 32 C above ambient. For commercial-grade 0C to +85C operation in a chassis with 55 C ambient inlet, total cooling margin is 28 C - adequate for most chassis but requires either heatsink or forced-air cooling. For industrial-grade EP2AGX95EF35I5N variants in extended-temperature environments, a finned heatsink with thermal interface material is recommended.
Three common pitfalls to avoid when designing with EP2AGX95EF35C6N: (1) Never apply VCCIO before VCC - this can cause irreversible damage due to I/O latch-up; follow Intel's Arria II GX handbook power-up sequence. (2) The C6 speed grade may fail timing closure at transceiver rates above 5 Gbps in dense designs; pre-compile timing estimates in Quartus II TimeQuest before committing PCB layout. (3) Configuration modes require correct MSEL[3:0] pin strapping for AS (Active Serial), PS (Passive Serial), JTAG, or FPP (Fast Passive Parallel); an incorrect MSEL strap prevents boot and requires hardware rework. Always verify MSEL with a logic analyzer during board bring-up.
Compliance Information
RoHS and REACH compliance per Intel material declaration. Pb-free terminal finish. Halogen-free mold compound. AEC-Q100 not applicable for FPGAs; automotive applications typically use EP2AGX95EF35I5N industrial-grade variant. NRND status (Not Recommended for New Designs) as of 2026-09-08 does not affect compliance.
