EP2AGX95EF35I3N - Arria II GX FPGA, 95K LE, 1152-FBGA | Intel
MPN: EP2AGX95EF35I3N ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1720 | $17,200.00 |
| 100 | $1580 | $158,000.00 |
| 500 | $1450 | $725,000.00 |
| 1,000 | $1320 | $1,320,000.00 |
EP2AGX95EF35I3N Overview
An FPGA is a reprogrammable semiconductor that implements arbitrary digital logic through configurable logic blocks (CLBs), programmable interconnects, and dedicated hard IP such as transceivers, DSP blocks, and memory controllers. Within the broader taxonomy, FPGAs belong to programmable logic devices, which sit alongside ASICs and CPLDs as alternatives to fixed-function ICs. Arria II GX sits in Intel's mid-range transceiver-equipped FPGA family, positioned between Cyclone (low-cost) and Stratix (high-performance) families, targeting cost-sensitive applications that still require multi-gigabit serial links.
Key features of the EP2AGX95EF35I3N include 4,747 LABs (logic array blocks), 6 embedded PLLs, 56 embedded 18x18 multipliers, and PCI Express hard IP blocks (x1/x4) for direct PCIe endpoint implementation. The device supports 1.4 Gbps LVDS, DDR3 SDRAM interfaces up to 800 MHz, and configuration via passive serial, fast passive parallel, or JTAG. Hard memory controllers simplify DDR3/DDR2/LPDDR2 memory subsystem design without consuming soft logic resources.
The Arria II GX architecture uses an 8-input adaptive logic module (ALM) per LE, providing finer-grained logic packing than previous generations. The 12 full-duplex transceiver channels support multiple protocols through programmable PCS blocks, enabling a single FPGA to bridge PCIe, CPRI, and Ethernet traffic simultaneously. Configuration bitstreams are AES-256 encrypted for IP protection.
Typical applications include wireless baseband processing, military radar and SIGINT systems, broadcast video processing, medical imaging, and industrial control with high-speed serial interfaces. The combination of mid-range logic density and integrated 3.75 Gbps transceivers makes the EP2AGX95EF35I3N well suited for protocol bridging, data aggregation, and DSP front-end designs.
When designing with this FPGA, allocate sufficient PCB area for the 1152-ball FC-FBGA package (35 mm body) and follow Intel's layout guidelines for transceiver channels - controlled-impedance differential traces, AC coupling capacitors, and reference clock distribution are mandatory for signal integrity. Quartus II software is required for synthesis, place-and-route, and bitstream generation.
This page consolidates distributor stock, cross-reference alternatives, and application guidance beyond the bare datasheet, helping engineers evaluate availability and replacement options for the EP2AGX95EF35I3N.
Drop-in alternatives for EP2AGX95EF35I3N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX95EF35I3N (same form factor and footprint) — differing in Package, PCIe Hard IP, Logic Elements, Process Technology, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2AGX95EF35I3
✅ Drop-In✓ In Stock
$1440 / Unit
View Datasheet →EP2AGX95EF35I3G
✅ Drop-In✓ In Stock
$280 / Unit
View Datasheet →EP2AGX95EF35C6N
✅ Drop-In✓ In Stock
$1390 / Unit
View Datasheet →EP2AGX95EF35C6G
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EP2AGX95EF35C6
✅ Drop-In✓ In Stock
$398 / Unit
View Datasheet →EP2AGX125EF35I3N
✅ Drop-In📋 Reference alternative (not in catalog)
EP2AGX95EF35I3N Maximum Ratings & Electrical Characteristics
| Family | Arria II GX |
| Logic Elements | 89,178 |
| Logic Array Blocks (LABs) | 3,747 |
| Embedded Memory | 4,518 Kbits |
| Embedded 18x18 Multipliers | 56 |
| User I/Os | 452 |
| Transceiver Channels | 12 (up to 3.75 Gbps) |
| Embedded PLLs | 6 |
| Core Voltage | 0.9 V |
| Process Technology | 40 nm |
| Package | 1152-ball FC-FBGA (EF35, 35 mm) |
| Operating Temperature | -40C to +100C (Industrial) |
| PCIe Hard IP | Yes (x1, x4 Gen1) |
| DDR3 Memory Interface | Up to 800 MHz |
| Configuration | Passive Serial / Fast Passive Parallel / JTAG |
| RoHS Status | Compliant |
EP2AGX95EF35I3N 1152-ball fc-fbga (ef35, 35 mm) Pin Configuration Guide
Pin configuration for EP2AGX95EF35I3N (1152-ball fc-fbga (ef35, 35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX95EF35I3N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX95EF35I3N is suitable for 6 applications: Wireless Baseband Processing, Military Radar and SIGINT Systems, Broadcast Video Processing, Medical Imaging Systems, Industrial Control and Protocol Bridging, Test and Measurement Instrumentation.
Wireless Baseband Processing
The EP2AGX95EF35I3N is well-suited for wireless baseband processing in 3G/4G remote radio heads and small cells, where its 12 transceiver channels at 3.75 Gbps support CPRI and OBSAI backhaul links directly. The 89,178 logic elements and 56 18x18 multipliers provide sufficient DSP capacity for uplink/downlink channelization, while the hard PCIe Gen1 IP enables direct baseband board-to-host communication. Designers typically pair the FPGA with DDR3 memory at 800 MHz for buffer storage, leveraging the hard memory controllers to preserve logic for signal processing. The industrial temperature grade ensures reliable operation in outdoor base station enclosures.
Recommended
Military Radar and SIGINT Systems
The EP2AGX95EF35I3N serves military radar, SIGINT, and electronic warfare applications where its combination of mid-range logic density and 3.75 Gbps transceivers enables digital down-conversion, beamforming, and high-speed ADC interface. With 4,518 Kbits of embedded memory and 56 multipliers, it can implement pulse compression, FFT, and matched-filter algorithms directly. The industrial temperature range meets MIL-spec ambient conditions for outdoor fielded systems. Designers implement sensor interfaces via LVDS (1.4 Gbps) and stream aggregated data over Serial RapidIO or custom serial links.
Recommended
Broadcast Video Processing
The EP2AGX95EF35I3N supports HD-SDI and 3G-SDI broadcast video routing, format conversion, and multiviewer applications through its 12 transceivers operating at 2.97 Gbps for SDI and 3.75 Gbps for general serial I/O. The 89K logic elements provide headroom for color space conversion, scaling, and overlay composition in multiviewer applications. The hard PCIe Gen1 IP enables host-based control and content insertion without consuming soft logic. The 1152-ball FC-FBGA package provides 452 user I/Os for parallel video interfaces and audio embedding/extraction logic.
Recommended
Medical Imaging Systems
The EP2AGX95EF35I3N is used in ultrasound, CT, and MRI imaging front-end processing, where its DSP blocks implement beamforming, FIR filtering, and image reconstruction. The 56 18x18 multipliers provide sufficient DSP throughput for real-time ultrasound beamforming across 64-128 channels, while the 4,518 Kbits of embedded memory supports line buffers and intermediate storage. Transceivers stream pre-processed data to host processors via PCIe Gen1, freeing the host CPU for image rendering. The industrial temperature grade supports imaging carts and portable diagnostic equipment.
Recommended
Industrial Control and Protocol Bridging
The EP2AGX95EF35I3N implements industrial protocol bridging between Gigabit Ethernet, Serial RapidIO, EtherCAT, PROFINET, and legacy fieldbus systems in factory automation and process control. With 12 transceivers at 3.75 Gbps, the FPGA can act as a multi-protocol gateway, translating between deterministic industrial networks. The 452 user I/Os accommodate parallel GPIO, SPI, and I2C peripherals, while the hard PCIe Gen1 IP enables slot-card integration into industrial PCs. The industrial temperature rating supports factory floor operation from -40C to +100C.
Recommended
Test and Measurement Instrumentation
The EP2AGX95EF35I3N provides real-time signal processing and high-speed data acquisition in oscilloscopes, logic analyzers, and protocol analyzers. The 12 transceivers accept multi-gigabit serial data streams and the 89K logic elements implement custom trigger logic, pattern matching, and protocol decoding. DDR3 memory at 800 MHz stores deep acquisition buffers, while PCIe Gen1 streams processed data to host analysis software. The 452 user I/Os provide parallel probe and front-panel interface bandwidth. Industrial temperature rating supports benchtop and rack-mount instrument deployment.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX95EF35I3N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX95EF35I3 | EP2AGX95EF35I3G | EP2AGX95EF35C6N | EP2AGX95EF35C6G | EP2AGX95EF35C6 | EP2AGX125EF35I3N |
|---|---|---|---|---|---|---|---|
| Package | 1152-ball FC-FBGA (EF35) | 1152-ball FC-FBGA (EF35) - same | 1152-ball FC-FBGA (EF35) - same | 1152-ball FC-FBGA (EF35) - same | 1152-ball FC-FBGA (EF35) - same | 1152-ball FC-FBGA (EF35) - same | 1152-ball FC-FBGA (EF35) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 89,178 | 89,178 | 89,178 | 89,178 | 89,178 | 89,178 | 124,700 (approximately) |
| Operating Temperature | -40C to +100C (Industrial) | -40C to +100C (Industrial) | -40C to +100C (Industrial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | -40C to +100C (Industrial) |
| Speed Grade | 3 | 3 | 3 | 6 | 6 | 6 | 3 |
| User I/Os | 452 | 452 | 452 | 452 | 452 | 452 | 452 |
| Transceiver Channels | 12 (up to 3.75 Gbps) | 12 (up to 3.75 Gbps) | 12 (up to 3.75 Gbps) | 12 (up to 3.75 Gbps) | 12 (up to 3.75 Gbps) | 12 (up to 3.75 Gbps) | |
| RoHS Compliance | Compliant (N suffix indicates Pb-free) | Compliant (standard) | Compliant (Pb-free, G suffix) | Compliant | Compliant (Pb-free) | Compliant (standard) | Compliant |
| Approximate Unit Price (qty-1, as of 2026-09-08) | $1,850 | Lower (tray vs tape-and-reel) | Slightly higher (Pb-free) | Lower (slower speed grade) | Lower (slower, Pb-free) | Higher (larger die) |
Key Differentiators
- Industrial temperature rating with speed grade 3 (faster timing) (vs EP2AGX95EF35C6N)
- Pb-free / RoHS-compliant lead finish (G suffix variant) (vs EP2AGX95EF35I3)
- Same EF35 package footprint enables easy density upgrade to 125K LEs (vs EP2AGX125EF35I3N)
Design Notes
Estimated: The 1152-ball FC-FBGA package has a 1.0 mm ball pitch on the EF35 land pattern. Designers must allocate at least a 12-layer PCB stackup to fan-out the ball grid and maintain 100 ohm differential impedance for the 12 transceiver channels. Use Intel's EF35 pin connection guidelines and follow the recommended via-in-pad or microvia escape pattern to avoid excessive stub lengths on high-speed serial signals.
Estimated: Transceiver channels operating at 3.75 Gbps require controlled-impedance differential routing with 100 ohm differential impedance, AC coupling capacitors (typically 100 nF) in series with each serial lane, and a clean reference clock input (differential LVPECL or LVDS) routed with impedance-matched traces. Use IBIS-AMI models from Intel for channel simulation before tape-out; signal integrity issues are the leading cause of first-board failures at multi-gigabit speeds.
Estimated: At maximum toggle rate across 89K logic elements with 12 active transceivers, the EP2AGX95EF35I3N can dissipate 5-8 W. The 1152-ball FC-FBGA package dissipates heat primarily through the die and balls, so designers should attach a thermal management solution (heatsink with thermal interface material or cold plate) and provide adequate airflow. Use the Arria II GX thermal model to simulate junction temperature under worst-case operating conditions and verify it stays below 100C at industrial ambient (85C) plus 15C margin.
Estimated: Do not confuse the EP2AGX95EF35I3N with the EP2AGX125EF35I3N - both share the same EF35 package footprint but have different logic capacities (89K vs 125K LEs). Configuration bitstreams are device-specific and Quartus II must target the correct device library. Also, ensure the configuration mode (Passive Serial, Fast Passive Parallel, or JTAG) is correctly selected via MSEL pins, and that the configuration clock source meets the minimum frequency requirement for the chosen mode.
Compliance Information
RoHS compliance indicated by 'N' suffix per Altera/Intel datasheet. AEC-Q100 not applicable (FPGA is not an automotive-qualified IC). Lead-free per N suffix. Halogen-free status not stated in available web data - set to unknown. REACH compliance assumed for Intel FPGA products.
