EP2S60F672C3NGA - Stratix II FPGA, 60K LEs, 672-FBGA | Intel
MPN: EP2S60F672C3NGA β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1450 | $1,450.00 |
| 10 | $1380 | $13,800.00 |
| 100 | $1290 | $129,000.00 |
| 500 | $1210 | $605,000.00 |
| 1,000 | $1150 | $1,150,000.00 |
EP2S60F672C3NGA Overview
An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit that combines configurable logic blocks (CLBs / LABs), programmable routing, embedded memory, and dedicated hard IP (transceivers, multipliers, PLLs) on a single die. FPGAs sit between general-purpose microcontrollers and ASICs in the design flexibility vs. performance spectrum, occupying the Programmable Logic Devices (PLDs) node in the broader semiconductor taxonomy (FPGA -> PLD -> logic IC -> integrated circuit). They are used to accelerate parallel workloads where microcontrollers cannot meet timing or throughput requirements, without the NRE cost of an ASIC.
Key features of the EP2S60F672C3NGA include 18 DSP blocks (each containing multiple 9x9 multipliers), dedicated external memory interfaces supporting DDR/DDR2/QDRII SRAM, up to 12 PLLs for clock management, and Adaptive Logic Modules (ALMs) that combine traditional LUT-based logic with register-rich arithmetic. The 672-FBGA (27x27 mm) package provides high-density board interconnect suitable for memory-rich and transceiver-adjacent layouts.
Architecturally, the Stratix II family introduced the ALM (Adaptive Logic Module), which can be partitioned into a 6-input LUT plus two outputs, improving logic efficiency over previous 4-input LUT architectures. The device operates from an internal core voltage of approximately 1.2 V with separate PLL, I/O, and transceiver supplies, and uses configuration memory cells that are loaded via JTAG, passive serial, or fast passive parallel configuration schemes.
Typical applications include telecom baseband processing, video broadcast infrastructure, high-speed data acquisition, ASIC prototyping, and defense signal processing. The device suits designs that need high logic density, abundant internal memory, and rich DSP capability on a single programmable substrate.
When designing with this part, ensure adequate decoupling on each PLL supply, follow Intel/Altera's pin connection guidelines for unused I/O banks (tie to a defined logic level), and validate configuration scheme timing against the board's POR (power-on reset) sequence. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP2S60F672C3NGA β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S60F672C3NGA (same form factor and footprint) β differing in Speed Grade, Package, Operating Temperature, PLLs, RoHS Status.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2S60F672C3N
β Drop-Inβ In Stock
$1175 / Unit
View Datasheet βEP2S60F672C3
β Drop-Inβ In Stock
$1033.14 / Unit
View Datasheet βEP2S60F67214N
β Drop-Inβ In Stock
$232 / Unit
View Datasheet βEP2S60F672C3NGA Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Process Technology | 90 nm |
| Logic Elements (LEs) | 60,440 |
| Logic Array Blocks (LABs) | 3,022 |
| Total RAM Bits | 2,544,192 |
| User I/O Pins | 492 |
| Package | 672-FBGA (FineLine BGA, 27x27 mm) |
| Core Voltage | 1.2 V (typical) |
| DSP Blocks | 18 blocks (multi 9x9 multipliers) |
| PLLs | Up to 12 |
| Mounting Type | Surface Mount |
| Configuration Mode | JTAG / Passive Serial / Fast Passive Parallel |
| Operating Temperature Grade | Commercial (0C to +85C) |
| RoHS Status | Compliant |
| Lifecycle | Not Recommended for New Designs (NRND) |
EP2S60F672C3NGA 672-fbga (fineline bga, 27x27 mm) Pin Configuration Guide
Pin configuration for EP2S60F672C3NGA (672-fbga (fineline bga, 27x27 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S60F672C3NGA.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S60F672C3NGA is suitable for 7 applications: Telecom Baseband Processing, ASIC Prototyping and Verification, Video Broadcast Infrastructure, High-Speed Data Acquisition, Industrial Motor Control and Drive, Defense Signal Processing (Radar/SIGINT), Medical Imaging (Ultrasound / CT Front-End).
Telecom Baseband Processing
The EP2S60F672C3NGA fits telecom baseband processing because its 60,440 logic elements and 18 DSP blocks provide the parallel arithmetic capacity needed for multi-carrier modulation, channel coding, and symbol-rate DSP. With 2,544,192 bits of embedded RAM, intermediate sample buffers and lookup tables (e.g., for QAM constellations) can be stored on-chip, reducing external memory accesses. The 12 PLLs allow independent clock domains for ADC sampling, fabric processing, and backhaul SERDES, while the 492 user I/Os support parallel LVDS links to RF front-ends. Quartus II provides telecom-grade IP (Turbo/Viterbi cores) targeting this device family.
Recommended
ASIC Prototyping and Verification
The EP2S60F672C3NGA is well suited as an ASIC prototyping vehicle because the Stratix II ALM (Adaptive Logic Module) architecture closely mirrors ASIC-style 6-input LUT partitioning, producing timing correlation that is meaningful for pre-silicon validation. 60K LEs accommodate mid-complexity ASICs, while 2.5 Mbit of embedded RAM captures line buffers, register files, and protocol state without external memory bottlenecks. Quartus II supports industry-standard interfaces (AXI, Avalon, DDR controllers) so the same RTL moves to ASIC synthesis with minimal IP re-mapping. The 672-FBGA package exposes enough pins to map ASIC pad-ring signals to the FPGA for full I/O verification.
Recommended
Video Broadcast Infrastructure
The EP2S60F672C3NGA suits video broadcast processing (SD/HD-SDI routing, compression pre-processing) thanks to its 492 user I/Os which carry parallel video buses and audio embedding channels. The 18 DSP blocks handle 9x9 multipliers for chroma interpolation, scaling, and de-interlacing filters in real time. With 2.5 Mbit of embedded RAM, line buffers and frame-delay FIFOs can be realized on-chip, eliminating external SRAM for many broadcast processing blocks. The 1.2 V core plus independent PLL supplies provide clean clocking for 148.5 MHz HD-SDI pixel clocks.
Recommended
High-Speed Data Acquisition
The EP2S60F672C3NGA serves high-speed data acquisition systems by providing 18 DSP blocks for real-time FIR/IIR filtering on ADC sample streams and 2.5 Mbit embedded RAM for capture buffers. The 12 PLLs derive multiple synchronized clocks for parallel ADC banks (e.g., LVDS ADCs sampling at 100-200 MSPS), while 492 user I/Os ingest multi-channel LVDS data without external serializers. Quartus II DDR2 controller IP lets designers pair the FPGA with commodity DDR2 memory for deep capture, with sustained bandwidth in the multi-GB/s range.
Recommended
Industrial Motor Control and Drive
The EP2S60F672C3NGA fits industrial motor drives because its 60K LEs execute field-oriented control (FOC), space-vector PWM, and current-loop compensation at the high PWM switching frequencies (10-50 kHz) used in industrial drives. The 18 DSP blocks accelerate Park/Clarke transforms and SVPWM math, while 2.5 Mbit embedded RAM captures diagnostic history (over-current events, fault traces) without external memory. The 492 I/Os interface to multi-axis encoder inputs (EnDat, Hiperface), gate-driver PWM outputs, and isolated SPI feedback from current sensors.
Recommended
Defense Signal Processing (Radar/SIGINT)
The EP2S60F672C3NGA supports radar/SIGINT preprocessing because the 18 DSP blocks implement parallel FFT butterflies and pulse-compression correlators at the data rates required for narrowband surveillance receivers. With 2.5 Mbit embedded RAM, range-bin and Doppler-bin buffers are kept on-chip, while 12 PLLs generate the staggered clocks needed for multi-channel coherent sampling. The 672-FBGA package's thermal performance (27x27 mm with central ground balls) supports sustained DSP operation. Quartus II supports MIL-STD-1553 and ARINC 429 IP cores for defense avionics integration.
Recommended
Medical Imaging (Ultrasound / CT Front-End)
The EP2S60F672C3NGA fits medical imaging front-ends because the 18 DSP blocks perform parallel beamforming, envelope detection, and Hilbert transforms across 32-128 ultrasound channels. The 492 user I/Os accept multi-channel LVDS ADC data streams from transducer arrays, while 2.5 Mbit embedded RAM acts as line buffers for scan conversion. The 12 PLLs derive the synchronized clocks required for coherent multi-channel sampling. Quartus II's deterministic fabric timing supports the low-latency response required for clinical-grade imaging.
Recommended
Recommended Products Summary
Engineering reference data for EP2S60F672C3NGA β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S60F672C3N | EP2S60F672C3 | EP2S60F67214N |
|---|---|---|---|---|
| Package | 672-FBGA (27x27 mm) | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 60,440 | 60,440 (same die) | 60,440 (same die) | 60,440 (same die) |
| Speed Grade | C3 | C3 - same | C3 - same | I4 (industrial grade, different speed bin) |
| Temperature Grade | Commercial (0C to +85C) | Commercial - same | Commercial - same | Industrial (-40C to +100C) |
| Embedded RAM | 2,544,192 bits | 2,544,192 bits (same die) | 2,544,192 bits (same die) | 2,544,192 bits (same die) |
| User I/O | 492 | 492 (same) | 492 (same) | 492 (same) |
| Lifecycle | NRND | NRND | NRND | NRND |
| DSP Blocks | 18 | 18 (same die) | 18 (same die) | 18 (same die) |
| Approx Unit Price (qty 1) | $1,450 USD | ~$1,450 USD (same silicon) | ~$1,450 USD (same silicon) | Higher (industrial grade) |
Key Differentiators
- Identical silicon with flexible packaging suffix (vs EP2S60F672C3)
- Industrial temperature option on same footprint (vs EP2S60F67214N)
- Same Quartus II tool flow as larger Stratix II parts (vs EP2S130F1508C3N)
Design Notes
The Stratix II EP2S60 requires multiple supply rails: VCCINT (1.2 V core), VCCIO (per-bank I/O voltage, 1.5/1.8/2.5/3.3 V), VCCA_PLL (1.5 V for analog PLL blocks), VCCD_PLL (1.2 V for digital PLL), and VCCPD (3.3 V for pre-drivers). Decoupling must follow Altera's recommended capacitor count (typically 30-50 ceramic caps of mixed values) placed as close as possible to the respective supply balls. Power-on sequencing requires VCCINT before VCCIO and VCCPD to avoid latch-up; the Power-on Reset (POR) circuit monitors this automatically but the supply ramp rates must stay within spec.
The 672-FBGA uses 1.0 mm ball pitch. PCB fabrication requires laser-drilled microvias or stacked-via construction, with controlled impedance (typically 50 ohm single-ended, 100 ohm differential) for high-speed LVDS pairs. Use the Intel/Altera Stratix II pin connection guidelines for unused I/O pins: tie unused I/O banks to a defined logic level through a resistor network, never leave them floating. Place configuration flash (EPCS64 or equivalent) within 2 inches of the FPGA's DCLK/ASDO/nCS pins to avoid signal integrity issues during configuration.
Estimated: at typical Stratix II EP2S60 utilization (60% LEs, 50% RAM, full DSP blocks running at 200 MHz), power dissipation is approximately 8-12 W. The 672-FBGA's exposed-die bottom must have thermal vias (0.3 mm pitch, 0.2 mm diameter) connecting the central ball grid to an internal copper plane. Use a heatsink with thermal interface material (TIM) for designs exceeding 8 W. Junction temperature must remain below 85 C for commercial grade; provide airflow if natural convection is insufficient.
Do not exceed VCCIO bank voltage when interfacing to mixed-voltage peripherals; the Stratix II VCCIO bank voltage must match or exceed the driven signal swing. Configuration pins (MSEL0, MSEL1, MSEL2) must be tied to VCCPD or GND with the correct values to select the configuration mode; floating MSEL pins can put the device in undefined states. JTAG TCK should be series-terminated at 33 ohm if TCK exceeds 6 inches. JTAG chain order matters when multiple devices share the chain; check BSDL files for correct TDI/TDO routing.
DDR2 memory interfaces require matched trace lengths within +/-25 mils and matched impedance of 50 ohm with 100 ohm differential for clock/strobe pairs. Use IBIS models from Intel/Altera for SI simulation; Stratix II output edge rates are sub-1 ns and require proper termination. SSO (Simultaneously Switching Outputs) limits per bank must be respected - typically 16-24 SSO per bank for LVTTL at 24 mA drive strength. Decoupling must be sized to handle SSO-induced supply droop without violating VCCIO tolerance.
Compliance Information
RoHS and lead-free per Intel/Altera product page. Not AEC-Q100 qualified (commercial grade). For automotive, evaluate AEC-Q100-qualified FPGAs from other families.
