EP2S90F1508C4 - 90K LE Stratix II FPGA, 1508-FCBGA | Altera
MPN: EP2S90F1508C4 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1725 | $17,250.00 |
| 100 | $1580 | $158,000.00 |
| 250 | $1450 | $362,500.00 |
| 500 | $1320 | $660,000.00 |
EP2S90F1508C4 Overview
A Field Programmable Gate Array (FPGA) is a type of integrated circuit that can be configured by the customer after manufacturing, containing an array of programmable logic blocks, programmable interconnect, and I/O pads. Stratix II FPGAs sit within the broader taxonomy of programmable logic devices (PLD), specifically as high-performance SRAM-based FPGAs (synthesizable ASIC replacement > ASIC-prototyping > high-end programmable logic > semiconductor). They are widely used for parallel DSP, packet processing, and protocol bridging, where deterministic latency and high logic density outperform fixed-function ASICs.
Key features of the EP2S90F1508C4 include up to 727 DSP blocks, dedicated high-speed transceivers for external memory interfaces, and hardened IP for DDR/DDR2 SDRAM and QDRII SRAM controllers. The architecture supports a multi-level routing fabric with row/column interconnect, and each LAB contains 10 Adaptive Logic Modules (ALMs) for efficient arithmetic and register packing. The 1508-ball FC-FBGA package exposes 902 user I/Os, making it suitable for systems requiring many parallel interfaces or wide external memory buses.
Typical applications include high-end ASIC prototyping, digital video broadcast encoders, telecom line-card packet processing, military radar signal processing, and test & measurement instrumentation. When designing with this device, ensure power-rail sequencing meets the Stratix II power-on-reset requirements and that the FC-BGA land pattern and via-in-pad stack-up match the Altera reference design. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EP2S90F1508C4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F1508C4 (same form factor and footprint) — differing in Package, Speed Grade, Operating Temperature Grade, Configuration Method, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S90F1508C4N
✅ Drop-In✓ In Stock
$1390 / Unit
View Datasheet →EP2S90F1508C3
✅ Drop-In✓ In Stock
$3719.39 / Unit
View Datasheet →EP2S90F1508C3N
✅ Drop-In✓ In Stock
$3200 / Unit
View Datasheet →EP2S130F1508C4
✅ Drop-In✓ In Stock
$1295 / Unit
View Datasheet →EP2S130F1508C4N
✅ Drop-In✓ In Stock
$4435.83 / Unit
View Datasheet →EP2S180F1508C4
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EP2S90F1508C4 Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Number of Logic Elements | 90,960 |
| Number of Logic Array Blocks (LABs) | 4,548 |
| Number of I/Os | 902 |
| Total Memory Bits | 4,520,488 |
| Process Technology | 90 nm CMOS |
| Core Voltage | 1.2 V |
| Maximum Operating Frequency | 711.24 MHz |
| Package | 1508-ball FC-FBGA |
| Mounting Type | Surface Mount (flip-chip BGA) |
| Operating Temperature Grade | Commercial |
| Configuration Method | SRAM-based, volatile |
| Lifecycle Status | Obsolete / EOL |
EP2S90F1508C4 1508-ball fc-fbga Pin Configuration Guide
Pin configuration for EP2S90F1508C4 (1508-ball fc-fbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F1508C4.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F1508C4 is suitable for 6 applications: ASIC Prototyping, Telecom Line-Card Packet Processing, Digital Video Broadcast Encoding, Military Radar Signal Processing, Test & Measurement Instrumentation, High-Speed Datapath Bridging.
ASIC Prototyping
The EP2S90F1508C4's 90,960 logic elements and 4,520,488 bits of embedded memory make it well-suited for ASIC prototyping where mid-to-high gate counts must be mapped onto a single device. With 902 user I/Os available on the 1508-ball FC-FBGA, it can absorb wide datapaths and many parallel external interfaces typical of pre-silicon validation. Designers typically place the EP2S90F1508C4 on a multi-FPGA prototyping board alongside companion Stratix II parts, partitioning the ASIC RTL across devices using time-domain multiplexing. The 711.24 MHz internal clock headroom supports prototyping of clock-heavy SoC blocks before tape-out. Trade-off: the 90 nm process consumes more power per LE than newer Stratix IV/V parts, so thermal envelope must be verified.
Recommended
Telecom Line-Card Packet Processing
The EP2S90F1508C4 supports telecom line-card designs where packet classification, queue management, and traffic shaping are implemented in parallel hardware. With up to 727 DSP blocks (per Stratix II family datasheet convention) and 902 user I/Os, the device can connect to multi-lane SGMII / SPI-4.2 / SFI-4 interfaces while maintaining deterministic pipeline latency. The 4,520 Kb embedded memory enables deep packet buffer pools without external SRAM. Designers route network PHY interfaces into the FPGA through LVDS or HSTL I/O standards configured in Quartus II. Compared with purpose-built NPUs, the EP2S90F1508C4 offers more flexibility for protocol updates at the cost of higher logic utilization.
Recommended
Digital Video Broadcast Encoding
The EP2S90F1508C4 handles DVB MPEG-2 / H.264 encoder workloads where pixel-rate processing pipelines must be parallelized across thousands of ALMs. Its 902 I/Os allow multiple SDI / HD-SDI inputs to be ingested simultaneously while 4,520 Kb of block memory provides line, macroblock, and motion-vector buffering. The 711 MHz internal clock supports real-time 1080p60 encode throughput when paired with dedicated motion-estimation IP. The 1508-ball FC-FBGA's 902 user I/Os are critical for multi-channel broadcast contribution encoders. Trade-off: the 90 nm process runs hotter than 40 nm Stratix IV, so chassis thermal design must budget for ~10-15 W per device at full utilization.
Recommended
Military Radar Signal Processing
Defense radar systems rely on the EP2S90F1508C4 for pulse-Doppler and SAR (Synthetic Aperture Radar) processing where high DSP block density and deterministic latency are non-negotiable. With 90K logic elements and the Stratix II DSP block architecture capable of 18x18 multiplications per clock cycle, the device sustains beam-forming and FFT pipelines at radar sample rates. The 902 user I/Os accommodate multi-channel ADC/DAC interfaces at LVDS rates, while embedded block memory stores range-Doppler maps. The 1508-ball FC-FBGA is preferred in ruggedized systems because flip-chip packages offer better thermal and vibration performance than wire-bond BGAs. Trade-off: the part is commercial grade; defense programs requiring MIL-STD-810 must re-qualify or specify the industrial-grade variant.
Recommended
Test & Measurement Instrumentation
The EP2S90F1508C4 forms the heart of high-end oscilloscopes, logic analyzers, and protocol testers where parallel sample acquisition and real-time waveform processing are required. Its 902 user I/Os can directly sample multi-channel probe data, while 4,520 Kb of embedded memory holds deep acquisition buffers before DMA to host. The 711 MHz internal clock supports real-time triggering on serial protocols like PCIe Gen1, SATA, or USB 2.0 when paired with the appropriate PHY. Designers typically integrate multi-gigabit transceivers (though Stratix II transceivers max at 6.375 Gbps, lower than newer families). The 1508-ball FC-FBGA enables dense probe-tip integration in modular instrument front-ends.
Recommended
High-Speed Datapath Bridging
Protocol-bridging cards use the EP2S90F1508C4 to translate between disparate I/O standards such as SPI-4.2 to PCIe, SFI to XAUI, or Aurora to Custom ASIC. Its 902 user I/Os can host multiple LVDS / HSTL / SSTL / LVCMOS buses simultaneously, eliminating discrete bridge chips. The 4,520 Kb embedded memory buffers packets between protocols of different clock domains. With Stratix II supporting dedicated SERDES rates up to 6.375 Gbps, the EP2S90F1508C4 can drive 10G Ethernet / OTU2 interfaces when paired with external PHYs. Trade-off: power consumption scales with active SERDES channels; estimate ~1 W per enabled transceiver at full utilization.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F1508C4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F1508C4N | EP2S90F1508C3 | EP2S130F1508C4 | EP2S180F1508C4 |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 1508-ball FC-FBGA | 1508-ball FC-FBGA - same | 1508-ball FC-FBGA - same | 1508-ball FC-FBGA - same | 1508-ball FC-FBGA - same |
| Logic Elements | 90,960 | 90,960 (same) | 90,960 (same) | 132,600 (+43%) | 179,400 (+97%) |
| Speed Grade | C4 (faster) | C4 (same) | C3 (slower, ~10-15%) | C4 (same) | C4 (same) |
| Lead-Free / RoHS | Standard (leaded) | Yes (Pb-free) | Standard (leaded) | Standard (leaded) | Standard (leaded) |
| User I/Os | 902 | 902 (same) | 902 (same) | 902 (same) | 902 (same) |
| Embedded Memory Bits | 4,520,488 | 4,520,488 (same) | 4,520,488 (same) | 6,747,840 (+49%) | 9,383,040 (+108%) |
| Core Voltage | 1.2 V | 1.2 V (same) | 1.2 V (same) | 1.2 V (same) | 1.2 V (same) |
| Maximum Clock Frequency | 711.24 MHz | 711.24 MHz (same) | ~600-650 MHz (C3 grade) | 711.24 MHz (same) | 711.24 MHz (same) |
Key Differentiators
- Direct drop-in compatibility with EP2S90F1508C4N (lead-free RoHS variant) (vs EP2S90F1508C4N)
- Pin-compatible higher-density upgrade path within Stratix II family (vs EP2S130F1508C4 / EP2S180F1508C4)
- Higher speed grade than C3 variant (vs EP2S90F1508C3)
Design Notes
The EP2S90F1508C4 requires multiple power rails (VCCINT 1.2 V core, VCCIO 1.2-3.3 V I/O, VCCP 1.2 V PLL, and VCCAUX 2.5 V). Per the Stratix II handbook, total quiescent + dynamic power at full utilization can exceed 15 W; design the PCB with at least 4 power layers and bulk decoupling of 220 uF per rail plus 0.1 uF / 10 nF high-frequency ceramics near each VCC pin group. Power-on sequencing must follow the Altera reference: VCCINT before VCCIO before VCCAUX, with monotonic ramp.
Estimated: with junction-to-ambient thermal resistance ~5 C/W (junction-to-case) for the 1508-ball FC-FBGA and ~12 C/W (junction-to-board) typical, the device at 15 W dissipation produces a junction-to-ambient rise of roughly 75 C above board temperature. A heatsink or cold-plate attachment is recommended for >10 W continuous operation. The flip-chip package has an integrated heat-spreader lid for direct thermal interface material (TIM) attachment.
The 1508-ball FC-FBGA requires via-in-pad (VIP) PCB technology with 0.5 mm pitch escape routing. Stack-up should be 8+ layers with controlled-impedance reference planes for LVDS/HSTL/SSTL signals. Use the Altera-provided land pattern and via template from the package specification document. Plane splits must avoid crossing LVDS pairs; keep the entire LVDS region on a single continuous GND/VCC plane.
Do not mix the EP2S90F1508C4 with later-generation Stratix IV/V parts on the same PCB unless the Quartus II pinout is re-mapped - the package ball assignments are not interchangeable across families despite similar 1508-ball FC-BGA substrates. Also note that the EP2S90F1508C4 is volatile (SRAM-based) and requires an external configuration device (EPCS or compatible) at every power-up; design the configuration flash footprint accordingly.
For external memory interfaces (DDR/DDR2 SDRAM, QDRII SRAM), follow the Altera EMIF pin-out guidelines with read/write deskew calibration. Place the memory devices within 50 mm of the FPGA edge I/Os and route byte lanes on the same PCB layer to avoid layer-transition delays. Use the Quartus II TimeQuest timing analyzer with board delay back-annotation to close timing across the 711 MHz internal clock domain.
Compliance Information
The base EP2S90F1508C4 is standard (leaded); lead-free RoHS-compliant variant is EP2S90F1508C4N. RoHS/REACH status was not specified in the verified web data and is marked unknown.
