EP2S90F1508C5N - Stratix II FPGA, 90K LE, 1508-FCBGA | Intel
MPN: EP2S90F1508C5N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4850 | $4,850.00 |
| 10 | $4650 | $46,500.00 |
| 100 | $4325 | $432,500.00 |
| 500 | $4050 | $2,025,000.00 |
| 1,000 | $3780 | $3,780,000.00 |
EP2S90F1508C5N Overview
An FPGA (Field-Programmable Gate Array) is a programmable logic device containing an array of configurable logic blocks (CLBs/LABs), programmable interconnect, and dedicated hard IP such as block RAM, DSP blocks, PLLs, and transceivers. FPGAs sit at the top of the programmable logic hierarchy, above CPLDs in density and capability, and serve as semi-custom silicon alternatives to ASICs. The Stratix II family was Altera's (now Intel FPGA) high-performance flagship at 90 nm, optimized for parallel processing and high-speed serial I/O for telecom, defense, and ASIC-replacement designs.
Key features include 4,548 Logic Array Blocks (LABs), 12 transceiver channels per bank (configurable up to differential LVDS), adaptive logic module (ALM) architecture for finer-grained logic packing, and DSP blocks delivering up to 384 GMACS throughput for fixed- and floating-point signal processing. The device supports DDR/DDR2/QDR memory interfaces via dedicated PHY blocks and offers remote-update configuration from external flash. It is implemented in a 1.0 mm pitch 1508-ball FCBGA package rated for the commercial 0 °C to +85 °C junction range.
The EP2S90F1508C5N variant carries the 'C' commercial temperature grade and speed grade '5' (the slowest Stratix II speed bin). Engineers should prefer speed grade '3' or '4' for designs that miss timing at grade '5'. The architecture pairs ALMs with TriMatrix memory blocks (MRAM, M4K, M512) and embedded DSP blocks, with PLLs and dedicated clock networks providing skew-managed global clocks.
Typical applications include high-speed DSP pipelines (radar, software-defined radio, baseband processing), ASIC prototyping, telecom line-card aggregation, high-end image and video processing, and 10 Gbps data-path bridging. The combination of 4,548 LABs and 902 I/Os makes it suitable for designs that aggregate many parallel channels.
When designing with the EP2S90F1508C5N, ensure the PCB accommodates the 1.0 mm-pitch 1508-ball FCBGA land pattern with microvia stack-up and matched-length clock traces. Use Altera/Intel Quartus II design software (legacy versions supported for Stratix II) for synthesis, place-and-route, and SignalTap II logic analysis. Multiple voltage rails (VCCINT, VCCIO, VCCAUX, VCC_PLL) require careful power-rail sequencing.
This page synthesizes distributor pricing, verified Stratix II family drop-in alternatives, and practical Quartus II design notes not consolidated in the original datasheet.
Drop-in alternatives for EP2S90F1508C5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F1508C5N (same form factor and footprint) — differing in Package, Speed Grade, Configuration Method, Operating Temperature, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S90F1508C5
✅ Drop-In✓ In Stock
$2590 / Unit
View Datasheet →EP2S90F1508C4N
✅ Drop-In✓ In Stock
$1390 / Unit
View Datasheet →EP2S90F1508C3N
✅ Drop-In✓ In Stock
$3200 / Unit
View Datasheet →EP2S90F1508C4
✅ Drop-In✓ In Stock
$1320 / Unit
View Datasheet →EP2S90F1508C3
✅ Drop-In✓ In Stock
$3719.39 / Unit
View Datasheet →EP2S90F1508C5N Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements | 90,960 |
| Logic Array Blocks (LABs) | 4,548 |
| User I/Os | 902 |
| Total Memory Bits | 4,520,488 |
| Operating Frequency Max | 609.76 MHz |
| Process Technology | 90 nm |
| Core Supply Voltage (VCCINT) | 1.2 V |
| Package | 1508-Ball FCBGA (FC-FBGA) |
| Ball Pitch | 1.0 mm |
| Temperature Grade | Commercial (C) |
| Speed Grade | 5 |
| Mounting Type | Surface Mount (Flip-Chip BGA) |
| Configuration Memory | SRAM-based, external flash support |
EP2S90F1508C5N 1508-ball fcbga (fc-fbga) Pin Configuration Guide
Pin configuration for EP2S90F1508C5N (1508-ball fcbga (fc-fbga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F1508C5N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F1508C5N is suitable for 6 applications: ASIC Prototyping and Emulation, High-Speed DSP Signal Processing, Telecom Line-Card Aggregation, Industrial Control and Test Equipment, High-End Image and Video Processing, Aerospace and Defense Signal Processing.
ASIC Prototyping and Emulation
The EP2S90F1508C5N's 90,960 logic elements and 4,520,488 bits of embedded memory make it a strong fit for ASIC prototyping where a large design must be partitioned across one or two FPGAs. Per the Stratix II datasheet, the 902 user I/Os and abundant TriMatrix memory blocks let prototyping teams map typical mid-complexity ASICs without time-multiplexing. The 1.0 mm-pitch FCBGA package and 90 nm process are well-characterized in legacy Quartus II flows, reducing bring-up risk versus migrating to newer families.
Recommended
High-Speed DSP Signal Processing
The EP2S90F1508C5N integrates dedicated DSP blocks delivering up to 384 GMACS, combined with 4.5 Mbits of TriMatrix memory for coefficient storage and delay lines. Per Intel Stratix II datasheet metrics, the 609.76 MHz internal DSP clock and 902 I/Os support multi-channel radar, software-defined radio, and baseband processing where parallelism matters more than per-channel clock rate. Compared with microcontrollers or DSP chips, this FPGA delivers true parallel pipeline architecture for sustained high-throughput filtering and FFT workloads.
Recommended
Telecom Line-Card Aggregation
Telecom line cards aggregate multiple lower-rate serial links into a backplane fabric, requiring both abundant I/O and deterministic timing. The EP2S90F1508C5N's 902 user I/Os accept dozens of LVDS pairs, while its PLLs and global clock networks provide skew-managed clocks for backplane serialization. Per Stratix II documentation, the device supports external DDR/DDR2/QDR memory interfaces for shared packet buffering. The C5 speed grade suits designs that meet timing conservatively; designers close on C3 or C4 if margins slip.
Recommended
Industrial Control and Test Equipment
Industrial test systems and high-channel-count data acquisition require FPGAs that combine many I/Os, parallel logic, and deterministic DSP for in-line signal conditioning. The EP2S90F1508C5N fits this profile with 902 I/Os for parallel ADC/DAC interfaces and embedded memory for sample buffering. Per the Stratix II datasheet, the device supports multiple I/O standards (LVTTL, LVCMOS, LVDS, SSTL) on a per-bank basis, simplifying mixed-voltage interfacing in industrial backplanes.
Recommended
High-End Image and Video Processing
Real-time image pipelines (machine vision, medical imaging, video broadcast) need high memory bandwidth and parallel pixel processing. The EP2S90F1508C5N's 4,520,488 embedded memory bits enable line-buffer and frame-buffer storage on-chip, while 902 I/Os interface to camera sensors and DDR2/QDR external memory. Per Stratix II datasheet figures, the DSP blocks can implement convolution and FFT kernels in dedicated silicon, leaving fabric logic free for control and formatting. Designers typically allocate one FPGA per image pipeline stage.
Recommended
Aerospace and Defense Signal Processing
Defense applications such as electronic warfare, radar front-end processing, and secure communications demand high logic density with proven reliability. The EP2S90F1508C5N family (commercial grade) handles development and ground systems; for flight hardware, designers migrate to the industrial-temperature EP2S90F1508I4N variant in the same 1508-ball FCBGA. Per Intel documentation, Stratix II supports security features like bitstream AES encryption (with licensing) and supports Conformal equivalence checking for DO-254-style verification flows.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F1508C5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F1508C5 | EP2S90F1508C4N | EP2S90F1508C3N | EP2S90F1508C4 | EP2S90F1508C3 |
|---|---|---|---|---|---|---|
| Package | 1508-Ball FCBGA | 1508-Ball FCBGA - same | 1508-Ball FCBGA - same | 1508-Ball FCBGA - same | 1508-Ball FCBGA - same | 1508-Ball FCBGA - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| User I/Os | 902 | 902 | 902 | 902 | 902 | 902 |
| Speed Grade | 5 (slowest) | 5 | 4 (faster) | 3 (fastest) | 4 (faster) | 3 (fastest) |
| RoHS / Pb-Free | Pb-free (N suffix) | Standard SnPb (non-N) | Pb-free (N suffix) | Pb-free (N suffix) | Standard SnPb (non-N) | Standard SnPb (non-N) |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Embedded Memory Bits | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 |
Key Differentiators
- Highest-density Stratix II device in commercial temperature grade (vs EP2S60F1020C5N)
- Same 1508-ball FCBGA footprint across full Stratix II family (vs EP2S180F1508C5N)
- Mature 90 nm process with extensive Quartus II tool support (vs Cyclone IV E EP4CE115F29)
Design Notes
The EP2S90F1508C5N in a 1508-ball FCBGA requires careful thermal management at full utilization. At typical Stratix II dynamic power figures (~10-20 W for 90% utilization at 200 MHz), the FCBGA needs a multi-layer PCB with thermal vias under the die and either forced-air cooling or a heat spreader. Refer to Intel Application Note AN 359 for Stratix II thermal design guidelines and junction temperature estimation.
The 1508-ball FCBGA uses a 1.0 mm ball pitch, which requires a PCB stack-up with microvias (laser-drilled) for fanout from inner balls. Standard through-via stack-ups will not work for break-out routing. Use at minimum a 4-1-4 stack-up with 0.5 oz copper on outer layers and 1 oz on inner, with via-in-pad or blind/buried vias for clean power delivery.
Stratix II EP2S90 devices require multiple supply rails: VCCINT (1.2 V core), VCCIO (per-bank I/O voltage, 1.5/1.8/2.5/3.3 V), VCCAUX (2.5 V auxiliary), VCC_PLL (1.2 V PLL analog), and VCC_CLKIN. Per the Stratix II datasheet, power-rail sequencing is required - VCCINT must ramp before or simultaneously with VCCAUX, and VCCIO banks should not be driven before VCCINT. Use a sequencer IC or disciplined PoL controller to meet these requirements.
Common design pitfalls include (1) omitting the external configuration flash for SRAM-based Stratix II - the FPGA does not retain configuration on power-down; (2) using Quartus Prime instead of Quartus II 13.0sp1 - Stratix II is not supported in Quartus Prime; (3) failing to decouple every VCCIO bank with 0.1 uF + bulk capacitors per the Stratix II PDN guidelines; (4) ignoring the JTAG chain when designing board test - include TCK/TMS/TDI/TDO test points for boundary-scan.
Stratix II differential I/O (LVDS) requires matched-length routing within the bank's skew budget (typically 100-200 mil on FR-4). Source-synchronous interfaces (DDR/DDR2/QDR) need write-leveling and DQ/DQS group matching. Use the Quartus II board-level IBIS models and run HyperLynx or Ansys SIwave simulations before committing to layout. Differential pairs should be 100 ohm differential impedance with 8-12 mil trace width on a 4-mil dielectric.
Compliance Information
RoHS compliance inferred from the 'N' suffix in EP2S90F1508C5N (Intel/Altera convention: N denotes Pb-free / RoHS-compliant finish). AEC-Q100 not applicable - FPGAs are not automotive-qualified per the standard. Halogen-free status not explicitly stated in retrieved web data; flagged as [DATA_NEEDED] in specs.
