EP2S90F1508C5 - 90k LE Stratix II FPGA 1508-FCBGA | Intel
MPN: EP2S90F1508C5 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3329.95 | $3,329.95 |
| 10 | $3170 | $31,700.00 |
| 100 | $2890 | $289,000.00 |
| 250 | $2740 | $685,000.00 |
| 500 | $2590 | $1,295,000.00 |
EP2S90F1508C5 Overview
An FPGA (Field Programmable Gate Array) is a semiconductor IC whose logic fabric, routing, and I/O can be reconfigured after manufacture via a hardware description language bitstream. Stratix II belongs to the high-performance FPGA family that sits hierarchically above CPLDs, DSPs, and general-purpose microcontrollers for parallel processing tasks, and it forms part of the broader programmable logic device (PLD) class within Intel's programmable solutions group. The 1508-pin FCBGA at 40 x 40 mm with 1 mm ball pitch targets high-I/O density board designs.
Key features include 12 transceiver channels, embedded TriMatrix memory blocks supporting up to 4.5 Mbit, dedicated DDR/DDR2 SDRAM and QDR II SRAM interfaces with PHY, 8 input phase-locked loops (PLLs), and a 36 x 36-bit embedded multiplier structure. The flexible signal standards support LVDS, LVPECL, SSTL, HSTL, and PCI/PCI-X via configurable I/O banks. Hot-socketing and partial reconfiguration are supported in-system.
Architecturally, the Stratix II fabric replaces the classic 4-input LUT of Stratix I with an adaptive logic module that combines two 4-LUTs and dedicated register chains, giving the device an effective logic density advantage. Row- and column-based interconnect, combined with direct-drive interconnect for high-fanout signals, delivers consistent timing closure at 500 MHz+ internal operation and 640 MHz memory interface rates typical of this -5 speed grade.
Typical applications include high-performance digital signal processing, ASIC prototyping, telecom line cards, video broadcasting infrastructure, and high-speed serial protocol bridging. The combination of embedded transceivers and abundant logic makes it equally suited for radar baseband, medical imaging pipelines, and test & measurement platforms.
When designing with this device, plan for a 1.2 V core and separate PLL/VCCIO analog supplies; the 1508-ball package requires careful BGA fanout, microvia stack-ups, and thermal vias to the 1.0 mm pitch pads. Bitstream encryption and JTAG-based configuration via the EPC device family or external flash should be reserved for production boots.
This page consolidates authorized distributor pricing, drop-in equivalents in the same 1508-FCBGA footprint, and practical PCB layout notes - engineering context not found in the manufacturer datasheet alone.
Drop-in alternatives for EP2S90F1508C5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F1508C5 (same form factor and footprint) — differing in Package, Speed Grade, Operating Temperature, Logic Array Blocks (LABs), Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S90F1508C5N
✅ Drop-In✓ In Stock
$3780 / Unit
View Datasheet →EP2S90F1508C4N
✅ Drop-In✓ In Stock
$1390 / Unit
View Datasheet →EP2S90F1508C4
✅ Drop-In✓ In Stock
$1320 / Unit
View Datasheet →EP2S130F1508C5
✅ Drop-In✓ In Stock
$345 / Unit
View Datasheet →EP2S180F1508C5
✅ Drop-In✓ In Stock
$4880 / Unit
View Datasheet →EP2S90F1508C3N
✅ Drop-In✓ In Stock
$3200 / Unit
View Datasheet →EP2S90F1508C5 Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements | 90,960 |
| Adaptive Logic Modules | 36,384 |
| Embedded Memory (bits) | 4,520,488 |
| Embedded DSP Blocks | 12 |
| Maximum User I/O | 902 |
| Package | 1508-ball FCBGA (FineLine BGA) |
| Package Size | 40 x 40 mm |
| Ball Pitch | 1.0 mm |
| Process Technology | 90 nm CMOS |
| Core Voltage | 1.2 V |
| Speed Grade | -5 (commercial) |
| Transceivers | 12 channels |
| PLLs | 8 |
| Operating Temperature | 0C to +85C (commercial) |
| Mounting Type | Surface Mount (BGA) |
EP2S90F1508C5 40 x 40 mm Pin Configuration Guide
Pin configuration for EP2S90F1508C5 (40 x 40 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F1508C5.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F1508C5 is suitable for 6 applications: ASIC Prototyping and Verification, Telecom Line-Card Interface Bridging, High-Performance DSP and Baseband Processing, Video Broadcasting and Image Processing, Test & Measurement Instrumentation, Industrial High-Speed Control and Motor Drive.
ASIC Prototyping and Verification
The EP2S90F1508C5 fits ASIC prototyping because it offers 90,960 logic elements and 4.5 Mbit of embedded memory in a single 1508-FCBGA, sufficient to map multi-million-gate ASIC netlists. With 12 transceiver channels and 8 PLLs, design teams can replicate the full I/O and clock structure of the target ASIC, then iterate firmware months before tape-out. Quartus II supports incremental compile, partition merge, and partial reconfiguration, allowing prototype bring-up that mirrors production silicon. Compared to running the same design on smaller FPGAs, the EP2S90 removes the need to split the design across multiple devices and avoids the cross-chip timing penalties that cost verification accuracy.
Recommended
Telecom Line-Card Interface Bridging
The EP2S90F1508C5 is widely deployed in telecom line cards that bridge between SERDES framer chips, network processors, and backplane SERDES links. Its 902 user I/O pins deliver ample LVDS/SSTL/HSTL signaling to fan out to multiple SFP/XFP cages and to a network processor's parallel interface. The 12 embedded transceivers run standard telecom data rates, while the 4.5 Mbit of TriMatrix memory buffers packets between ingress and egress flows. Using the dedicated DDR/DDR2/QDR II PHY, the FPGA can attach directly to external SRAM/QDR memories used for lookup-table caching, reducing the BOM versus a discrete memory controller. In production the part serves as a glue-logic replacement for multiple CPLDs and ASIC bridge chips.
Recommended
High-Performance DSP and Baseband Processing
The EP2S90F1508C5 suits high-performance DSP workloads because it integrates 12 dedicated DSP blocks delivering up to 568 GMACs of throughput, paired with 36 x 36-bit embedded multipliers for FIR, FFT, and matrix operations. At its -5 speed grade the device supports internal clock rates above 300 MHz and memory interfaces up to 640 MHz, suitable for radar baseband, software-defined radio, and medical imaging pipelines. The combination of abundant logic, DSP, and embedded memory lets designers collapse what previously required an FPGA plus a DSP co-processor into a single chip, simplifying board layout and reducing power. Quartus II's DSP Builder toolchain maps MATLAB/Simulink designs directly into the fabric.
Recommended
Video Broadcasting and Image Processing
The EP2S90F1508C5 fits professional video broadcasting because its 902 user I/O can drive multiple parallel RGB/YCbCr video interfaces, SDI serializers, and HDMI/DVI bridges simultaneously. The 4.5 Mbit embedded memory acts as line and frame buffers for de-interlacing, scaling, and color-space conversion, while 12 DSP blocks handle real-time video processing kernels such as 2D filtering and motion compensation. Designers can implement multi-channel processing - for example 4 channels of 1080p60 - inside a single device, avoiding multi-FPGA partitioning. Compared to using a DSP plus external memory, the integrated memory and DDR PHY simplify PCB routing and shorten development cycles for broadcast OEM customers.
Recommended
Test & Measurement Instrumentation
The EP2S90F1508C5 is well suited to high-end test and measurement instruments such as logic analyzers, protocol exercisers, and arbitrary waveform generators because it combines 902 I/O pins for parallel stimulus/capture with 12 high-speed transceivers for serial protocol triggering. Its 8 PLLs and flexible clock networks allow multiple independent sample-rate domains, while the embedded TriMatrix memory holds deep capture buffers between trigger events. The -5 speed grade supports internal logic at 500 MHz+ so designers can implement pattern generation at rates that previously demanded custom ASICs. Compared to discrete TTL/ECL logic, the FPGA delivers design reusability across product generations.
Recommended
Industrial High-Speed Control and Motor Drive
The EP2S90F1508C5 supports industrial motion-control applications because its abundant LVDS I/O and flexible PLL clocking can simultaneously drive multi-axis encoder feedback, PWM outputs to IGBT/MOSFET gate drivers, and safety-rated communication interfaces such as EtherCAT, Profinet, or SERCOS III. The 4.5 Mbit embedded memory holds trajectory tables and PID state for closed-loop control, while the DSP blocks accelerate field-oriented control (FOC) math at update rates above 100 kHz. Industrial designers also value the device's deterministic timing closure - critical for sub-microsecond control loops. Compared to discrete DSP + CPLD solutions, the FPGA consolidates logic and reduces board area, easing EN 61800 compliance verification.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F1508C5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F1508C5N | EP2S90F1508C4N | EP2S90F1508C4 | EP2S130F1508C5 | EP2S180F1508C5 | EP2S90F1508C3N |
|---|---|---|---|---|---|---|---|
| Package | 1508-ball FCBGA (40x40 mm) | 1508-ball FCBGA (40x40 mm) - same | 1508-ball FCBGA (40x40 mm) - same | 1508-ball FCBGA (40x40 mm) - same | 1508-ball FCBGA (40x40 mm) - same | 1508-ball FCBGA (40x40 mm) - same | 1508-ball FCBGA (40x40 mm) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 132,540 | 179,400 | 90,960 |
| Embedded Memory (Mbit) | 4.5 | 4.5 | 4.5 | 4.5 | 6.7 | 9.4 | 4.5 |
| Speed Grade | -5 (commercial) | -5 | -4 | -4 | -5 | -5 | -3 |
| Pin/Ball Count | 1508 | 1508 | 1508 | 1508 | 1508 | 1508 | 1508 |
| Lifecycle Status | last_time_buy | last_time_buy | last_time_buy | last_time_buy | last_time_buy | last_time_buy | last_time_buy |
Key Differentiators
- Highest-density 90k LE Stratix II option on 1508-FCBGA (vs EP2S60F1508C5)
- Same-footprint upgrade path to 132k LEs and 180k LEs (vs EP2S130F1508C5 / EP2S180F1508C5)
- 902 user I/O for high-density parallel interfaces (vs EP2S90F1020C5 (1020-ball FCBGA))
Design Notes
Estimated: the 1508-ball FCBGA at 1.0 mm pitch requires a high-density PCB stack-up - 8+ layer board with stacked microvias to escape the inner rows. Plan at least 4 routing layers plus dedicated power/ground planes; the Intel Stratix II Handbook (AN 359) recommends a 1-2-1 or 1-2-2-1 stack-up for signal integrity at the 640 MHz memory interface rate. Use thermal vias on the BGA land pattern to keep junction temperature below 100C under typical workloads.
Estimated: budget for a 1.2 V core supply at up to 2.5 A under peak loading (VCCINT), separate PLL analog 1.2 V (VCC_PLL), and per-bank VCCIO supplies. Stratix II requires power-on sequencing: VCCINT must rise before or simultaneous with VCCIO; consult the device handbook for the exact monotonic ramp requirement. Add bulk decoupling of at least 220 uF low-ESR polymer plus 0.1 uF / 1 uF / 10 uF ceramics distributed around the BGA periphery.
Common pitfalls on EP2S90F1508C5 designs include: (1) omitting the JTAG pull-up on TCK/TMS/TDO - causes configuration failure; (2) using the wrong configuration scheme (the device defaults to fast passive parallel, requiring an external configuration controller); (3) ignoring MSL3 floor-life rules, which require dry-pack handling and pre-bake if seal is broken; (4) under-estimating the Quartus II compile time, which can exceed 2 hours on full-fabric builds; (5) selecting the wrong device in Quartus (EP2S90 vs EP2S90E vs EP2S90F variants differ in transceiver count). Always validate the bitstream on a development kit before committing to board spin.
Estimated: at full logic utilization with 12 transceivers active, the EP2S90F1508C5 can dissipate 8-12 W. The FCBGA-1508 package has a theta_JA around 12-15 C/W on a standard 8-layer board, so junction temperature rise is roughly 100-180 C above ambient. Mount a heatsink or use forced-air cooling if the system operates above 50C ambient; otherwise device may throttle or trigger thermal protection. Use the on-die TEMP diode (TDIOD/TDIOP pins) with a MAX1619 or similar external sensor for thermal monitoring.
Compliance Information
RoHS/REACH compliance for EP2S90F1508C5 (non-N suffix) not explicitly confirmed by verified web data; the EP2S90F1508C5N variant carries lead-free ball finish per FindIC cross-reference. Confirm at order entry with the authorized distributor.
