EP610PC-35 - 16-Macrocell Classic EPLD, 35ns tPD | Rochester
MPN: EP610PC-35 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $25.83 | $25.83 |
| 10 | $23.25 | $232.50 |
| 100 | $20.66 | $2,066.00 |
| 500 | $18.59 | $9,295.00 |
| 1,000 | $16.79 | $16,790.00 |
EP610PC-35 Overview
A Classic EPLD is a programmable logic device from the first generation of CMOS PLDs, combining macrocell-based logic, deterministic timing, and non-volatile (UV-erasable) configuration. EP610-class parts sit in the broader taxonomy of programmable logic devices (PLDs), which include simple PAL/GAL devices at the low end, CPLDs in the middle, and FPGAs at the high end. EP610PC-35 belongs to the low-density CPLD/EPLD tier, suitable for glue logic, address decoding, bus arbitration, and state-machine replacement in industrial, military, and avionics systems designed in the late 1980s and 1990s.
Key features include 16 macrocells, 300 gates of usable logic, 35ns worst-case tPD, 100 MHz internal fCNT, 5V ±5% supply operation, and JEDEC-standard 24-pin PDIP packaging. The device supports synchronous and asynchronous clocking, programmable I/O architecture with output enable, and a 100% factory-tested AC performance specification. The -35 speed grade positions this part at the slower end of the EP610 family; faster -25 and -20 grades exist for timing-critical paths.
Technically, the EP610 family uses a Classic macrocell architecture with sum-of-products logic feeding a programmable output register. The 24-pin PDIP footprint is a JEDEC-standard 0.600" wide plastic DIP with through-hole leads, making the EP610PC-35 suitable for socketed designs, hand-prototyping breadboards, and legacy board repair. Parts are tested and re-qualified by Rochester Electronics against the original Altera specifications to provide form-fit-function continuity.
Typical applications include legacy industrial control replacement, address decoding for 8/16-bit microprocessor buses, state-machine implementation for instrumentation, and pin-compatible second-source for end-of-life designs. The UV-erasable window variant (EP610DC) and one-time-programmable plastic versions share the same logic and timing.
When designing with this part, note that it is not pin-compatible with modern low-voltage CPLDs (3.3V or 1.8V). Use it only where 5V I/O, original Altera EP610 footprints, or long-term military/industrial sustainment programs require it. Modern low-cost alternatives from Lattice (GAL/iCE40) require PCB rework.
This page synthesizes distributor pricing, Rochester sustainment lead times, and practical cross-references not found in the original Altera datasheet, with drop-in alternatives sourced from verified EP610-family listings.
Drop-in alternatives for EP610PC-35 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610PC-35 (same form factor and footprint) — differing in Package, Propagation Delay (tPD), Supply Voltage (VCC), RoHS Status, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610PC-30
✅ Drop-In✓ In Stock
$27.74 / Unit
View Datasheet →EP610PC-25
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EP610PC-20
✅ Drop-In✓ In Stock
$47.8 / Unit
View Datasheet →EP610DC-35
✅ Drop-In✓ In Stock
$18.4 / Unit
View Datasheet →EP610PC-35 Maximum Ratings & Electrical Characteristics
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Family | Classic EPLD |
| Macrocells | 16 |
| Usable Gates | 300 |
| Propagation Delay (tPD) | 37 ns (max, -35 speed grade) |
| Internal Counter Frequency | up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Supply Voltage - Internal | 4.75 V to 5.25 V |
| Operating Temperature | 0C to +70C (commercial) |
| Programmable Type | EPLD (UV-erasable window variant: EP610DC; plastic OTP) |
| Package | 24-pin PDIP (Plastic DIP, 0.600" wide, through-hole) |
| Mounting Type | Through Hole |
| Supplier Device Package | 24-PDIP |
| Logic Family | CMOS |
EP610PC-35 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 2 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 3 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 4 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 5 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 6 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 7 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 8 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 9 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 10 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 11 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 12 | GND — Ground reference (0 V) |
| Pin 13 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 14 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 15 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 16 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 17 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 18 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 19 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 20 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 21 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 22 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 23 | I/O — Bidirectional I/O pin / macrocell input |
| Pin 24 | VCC — +5V supply input |
Typical Applications
EP610PC-35 is suitable for 6 applications: Legacy 5V Glue Logic Replacement, Microprocessor Address Decoding, Industrial Control State Machines, Avionics & Military Sustainment, Test & Measurement Instrumentation, Pin-Compatible Legacy Repair.
Legacy 5V Glue Logic Replacement
The EP610PC-35's 16 macrocells and 5V supply make it well suited for glue-logic replacement in legacy 5V systems originally designed around the Altera Classic EPLD family. Its 37ns tPD comfortably handles address decoding, chip-select generation, and bus-arbitration logic at microprocessor speeds up to roughly 25 MHz. Replacing TTL/CMOS 74-series glue with one EPLD reduces board area and improves reliability by replacing dozens of discrete gates with a single programmable device. The 24-pin PDIP footprint fits standard through-hole prototyping boards and existing footprints, enabling one-to-one board-level repair of out-of-production equipment without PCB rework.
Recommended
Microprocessor Address Decoding
The EP610PC-35 is widely used for address decoding in 8-bit and 16-bit microprocessor systems where its 16 macrocells can implement multiple chip-select decode equations in a single device. With a 37ns tPD, the part adds approximately 37ns of propagation delay to chip-select signals, well within budget for systems running at 8-25 MHz. The 5V supply and TTL-compatible I/O levels match legacy 8080, 8085, Z80, 68k, and 8086 bus interfaces directly without level shifters. The plastic OTP packaging is appropriate for production volumes where design changes are unlikely, while the CERDIP version (EP610DC-35) supports prototype development.
Recommended
Industrial Control State Machines
The EP610PC-35 implements reliable state machines for industrial control applications including conveyor sequencing, machine-tool control, and process automation. Its 16 macrocells comfortably encode 8-state to 32-state FSMs with output combinational logic, while the 5V CMOS design provides good EMC immunity in electrically noisy factory environments. The 0C to +70C commercial temperature range is suitable for most factory-floor installations, and Rochester Electronics' sustained-manufacturing program guarantees long-term parts availability for equipment with 15-25 year service lives. The through-hole PDIP package also simplifies field service and board-level repair.
Recommended
Avionics & Military Sustainment
The EP610PC-35 (and its military-screened variant EP610DM/883B) is a QML-sustained component used in legacy avionics, military communications, and defense electronics where form-fit-function continuity with the original Altera EP610 is mandatory. Rochester Electronics specifically manufactures the EP610PC-35 to support long-life-cycle defense programs where the original Altera production has ended but fielded systems still require spare parts. The plastic PDIP package offers a cost-effective option for non-flight-grade spare parts, while the ceramic DIP versions provide hermeticity for flight hardware. MIL-STD-883 screening is available on the EP610DM variants.
Recommended
Test & Measurement Instrumentation
The EP610PC-35 is used in legacy test and measurement instruments for custom timing generators, pulse-pattern logic, and front-panel interface decoding. Its deterministic 37ns tPD provides predictable timing paths critical for instrument calibration, and its 5V CMOS I/O drives standard TTL instrumentation busses directly. The Classic EPLD architecture supports real-time reprogramming (with the CERDIP EP610DC-35 variant) during instrument development, while production builds use the lower-cost plastic OTP EP610PC-35. The 24-pin PDIP fits standard instrument card-cage form factors used in 1980s-1990s era ATE.
Recommended
Pin-Compatible Legacy Repair
The EP610PC-35 is the canonical form-fit-function replacement for end-of-life Altera EP610PC-35 sockets in production equipment where redesign is not feasible. Its identical 24-pin PDIP pinout, 5V supply, and Classic EPLD macrocell architecture mean it can be dropped into existing Altera EP610 sockets without any board modification. This makes it the part of choice for sustaining avionics, industrial process control, telecommunications, and military systems originally built with Classic EPLDs in the late 1980s and 1990s. Rochester Electronics specifically tests these parts to original Altera specifications to guarantee electrical and timing compatibility.
Recommended
Recommended Products Summary
Engineering reference data for EP610PC-35 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610PC-30 | EP610PC-25 | EP610PC-20 | EP610DC-35 |
|---|---|---|---|---|---|
| Package | 24-pin PDIP | 24-pin PDIP (same) | 24-pin PDIP (same) | 24-pin PDIP (same) | 24-pin CERDIP (same footprint, ceramic body) |
| Brand | Rochester Electronics | Rochester Electronics (same) | Rochester Electronics (same) | Rochester Electronics (same) | Rochester Electronics (same) |
| Propagation Delay (tPD) | 37 ns | 30 ns (19% faster) | 25 ns (32% faster) | 20 ns (46% faster) | 37 ns (identical) |
| Macrocells | 16 | 16 (same) | 16 (same) | 16 (same) | 16 (same) |
| Usable Gates | 300 | 300 (same) | 300 (same) | 300 (same) | 300 (same) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V (same) | 4.75 V to 5.25 V (same) | 4.75 V to 5.25 V (same) | 4.75 V to 5.25 V (same) |
| Program Type | OTP (plastic) | OTP (plastic) | OTP (plastic) | OTP (plastic) | UV-erasable (windowed ceramic) |
| Internal Counter Frequency | up to 100 MHz | up to 100 MHz | up to 100 MHz | up to 100 MHz | up to 100 MHz |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
Key Differentiators
- Slowest (lowest-cost) grade in EP610PC family (vs EP610PC-25)
- Plastic OTP vs ceramic UV-erasable packaging (vs EP610DC-35)
- Through-hole PDIP vs modern surface-mount CPLD packages (vs Modern Lattice/Xilinx CPLDs)
Design Notes
Estimated: The EP610PC-35 is NOT pin-compatible with modern 3.3V or 1.8V CPLDs (Lattice iCE40, Xilinx CoolRunner, etc.). Engineers migrating legacy 5V designs to lower-voltage logic MUST redesign the PCB footprint, add level shifters, and rewrite the logic (Classic EPLD vs modern LUT-based architectures). Assuming drop-in compatibility is the single most common design pitfall when working with EP610-class parts.
The 24-pin PDIP package follows the JEDEC-standard 0.600" wide through-hole DIP with 2.54mm (100 mil) pin pitch. When designing a new PCB that uses the EP610PC-35, provide a 24-pin DIP socket (machined-pin or economy-pin IC socket) to allow easy programming and replacement. Decoupling: place a 0.1 uF ceramic bypass capacitor directly between VCC (pin 24) and GND (pin 12), with trace lengths kept under 5mm to minimize power-rail inductance.
The 37ns tPD of the EP610PC-35 is at the slower end of the EP610 family and is adequate for legacy 8/16-bit microprocessor buses operating below 25 MHz. For designs requiring faster address decoding or state-machine response, choose the EP610PC-25 (25ns) or EP610PC-20 (20ns) which are drop-in compatible. Output drive strength is standard TTL (typically ±4 mA IOL, -1 mA IOH) - sufficient for directly driving one or two TTL loads but verify fanout if driving bus-heavy backplanes.
Estimated: The EP610PC-35 in a 24-pin PDIP package dissipates approximately 200-400 mW typical depending on switching activity and output loading. Junction-to-ambient thermal resistance (theta_JA) for PDIP-24 is approximately 50-60 C/W in still air. No heatsink is required for normal operation; however, in sealed enclosures with elevated ambient temperature, derate by ensuring case temperature stays below 70C commercial limit. The ceramic DIP variant (EP610DC-35) has slightly better thermal performance (~45 C/W) due to its ceramic body.
Compliance Information
RoHS/REACH compliance not confirmed in provided data; the plastic PDIP-24 package historically contains lead (SnPb) finish typical of 1980s-1990s Altera EPLDs. Military-screened EP610DM/883B variant is available for MIL-PRF-38535 QML applications. AEC-Q100 is not applicable - the part is a legacy programmable logic device, not an automotive-qualified IC.
