EP910ILC-15 - 24 Macrocells, 66.6MHz CPLD | Altera Classic Family
MPN: EP910ILC-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.75 | $247.50 |
| 100 | $21.2 | $2,120.00 |
| 500 | $18.4 | $9,200.00 |
| 1,000 | $16.1 | $16,100.00 |
EP910ILC-15 Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the architecture flexibility of a PLD with the density of a small FPGA. In the system-on-chip hierarchy, a CPLD sits between discrete 74-series logic gates and an FPGA, offering deterministic timing, instant-on behavior, and pin-to-pin compatibility across logic density variants. The EP910 family belongs to the legacy Classic EPLD line that pre-dates the modern MAX series and is now maintained by Rochester Electronics as a long-life product.
Key features of the EP910ILC-15 include 24 macrocells, 36 user I/O pins, 15 ns pin-to-pin propagation delay (tPD), a maximum internal operating frequency of approximately 83.33 MHz, and zero standby power. The device integrates an on-chip programmable interconnect, a JTAG-compatible test interface for in-system verification, and supports 5V CMOS or TTL input/output levels. The EPROM cell technology provides non-volatile configuration that retains state through power cycles without an external boot PROM.
Architecture-wise, the EP910 family is built on a CMOS EPROM process with a sum-of-products logic structure feeding into a fixed OR array. Each macrocell contains a programmable flip-flop, output enable, and feedback path. The device supports logic synthesis through the MAX+PLUS II development environment (legacy tool flow), and parts can be re-programmed by exposing the package window to UV light for approximately 20 minutes followed by re-loading of the JEDEC fuse map.
Typical applications of the EP910ILC-15 include glue-logic replacement for 74LS/74HC discrete gates, address decoding in legacy 8-bit and 16-bit microprocessor systems, bus interfacing between asynchronous peripherals and main processors, state-machine control of electromechanical subsystems, and prototyping platforms for verification of synchronous logic prior to ASIC tape-out.
When designing with this part, remember that the PLCC-44 package requires a through-hole socket or careful reflow profile, and that the 15ns grade targets 66.6MHz system clocks rather than high-speed DSP pipelines. For new designs, verify whether the contemporary MAX V or MAX 10 CPLD families can deliver equivalent logic density at lower standby current.
This page synthesizes Rochester Electronics authorized stocking information, Altera datasheet parametric excerpts, and practical drop-in alternatives not found in the original manufacturer datasheet - enabling faster procurement decisions for long-life-cycle industrial programs.
Drop-in alternatives for EP910ILC-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910ILC-15 (same form factor and footprint) — differing in Package, Family, Operating Temperature, Mounting Type, Supply Voltage (VCC).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910ILC-12
✅ Drop-In✓ In Stock
$12.4 / Unit
View Datasheet →EP910ILC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP910IDC-15
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP910DC-15
✅ Drop-In✓ In Stock
$10.75 / Unit
View Datasheet →EP910LC-30T
✅ Drop-In✓ In Stock
$7.1 / Unit
View Datasheet →EP910DI-35
✅ Drop-In✓ In Stock
$35.2 / Unit
View Datasheet →EP910ILC-15 Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD |
| Series | EP910 |
| Logic Gates | 450 |
| Macrocells | 24 |
| User I/O Pins | 36 |
| Propagation Delay (tPD) | 15 ns |
| Maximum Operating Frequency | 83.33 MHz |
| Supply Voltage | 5 V |
| Memory Type | EPROM (UV-erasable) |
| Operating Temperature | -40C to +85C (industrial) |
| Package | 44-pin PLCC (J-lead) |
| Mounting Type | Surface Mount (SMT) |
| Propagation Class | -15 speed grade |
| Storage Condition | Dry cabinet, humidity-controlled |
EP910ILC-15 Pin Configuration
| Pin 1 | VCC — 5V power supply |
| Pin 2 | I/O — User I/O pin (macrocell) |
| Pin 3 | I/O — User I/O pin (macrocell) |
| Pin 4 | I/O — User I/O pin (macrocell) |
| Pin 5 | I/O — User I/O pin (macrocell) |
| Pin 6 | I/O — User I/O pin (macrocell) |
| Pin 7 | I/O — User I/O pin (macrocell) |
| Pin 8 | I/O — User I/O pin (macrocell) |
| Pin 9 | I/O — User I/O pin (macrocell) |
| Pin 10 | I/O — User I/O pin (macrocell) |
| Pin 11 | I/O — User I/O pin (macrocell) |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — User I/O pin (macrocell) |
| Pin 14 | I/O — User I/O pin (macrocell) |
| Pin 15 | I/O — User I/O pin (macrocell) |
| Pin 16 | I/O — User I/O pin (macrocell) |
| Pin 17 | I/O — User I/O pin (macrocell) |
| Pin 18 | I/O — User I/O pin (macrocell) |
| Pin 19 | I/O — User I/O pin (macrocell) |
| Pin 20 | I/O — User I/O pin (macrocell) |
| Pin 21 | I/O — User I/O pin (macrocell) |
| Pin 22 | I/O — User I/O pin (macrocell) |
| Pin 23 | I/O — User I/O pin (macrocell) |
| Pin 24 | GND — Ground |
| Pin 25 | I/O — User I/O pin (macrocell) |
| Pin 26 | I/O — User I/O pin (macrocell) |
| Pin 27 | I/O — User I/O pin (macrocell) |
| Pin 28 | I/O — User I/O pin (macrocell) |
| Pin 29 | I/O — User I/O pin (macrocell) |
| Pin 30 | I/O — User I/O pin (macrocell) |
| Pin 31 | I/O — User I/O pin (macrocell) |
| Pin 32 | I/O — User I/O pin (macrocell) |
| Pin 33 | I/O — User I/O pin (macrocell) |
| Pin 34 | I/O — User I/O pin (macrocell) |
| Pin 35 | I/O — User I/O pin (macrocell) |
| Pin 36 | I/O — User I/O pin (macrocell) |
| Pin 37 | TDI — JTAG Test Data In |
| Pin 38 | TMS — JTAG Test Mode Select |
| Pin 39 | TCK — JTAG Test Clock |
| Pin 40 | TDO — JTAG Test Data Out |
| Pin 41 | I/O — User I/O pin (macrocell) |
| Pin 42 | I/O — User I/O pin (macrocell) |
| Pin 43 | GND — Ground |
| Pin 44 | VCC — 5V power supply |
Typical Applications
EP910ILC-15 is suitable for 6 applications: 74-Series Glue Logic Replacement, Address Decoding in Legacy 8/16-bit Microprocessor Systems, Bus Interface Logic Between Asynchronous Peripherals, State-Machine Control of Electromechanical Subsystems, ASIC Prototyping Verification Platform, Legacy Aerospace & Defense Avionics Systems.
74-Series Glue Logic Replacement
The EP910ILC-15 consolidates 4-8 discrete 74LS/74HC logic gates into a single programmable device, reducing PCB area by 60-80%. With 24 macrocells providing 450 usable gates and 15ns tPD supporting 66.6MHz operation, the part replaces random SSI/MSI logic that historically consumed 4-6 SOIC packages. Its 5V CMOS/TTL compatible I/O and JTAG-driven programming make it ideal for industrial control boards where board space is constrained and 5V rails remain standard. The EP910's instant-on EPROM configuration eliminates boot-time delays typical of SRAM-based FPGAs.
Recommended
Address Decoding in Legacy 8/16-bit Microprocessor Systems
The EP910ILC-15 implements full address decoding for legacy 8086/68000/Z80 microprocessor systems where chip-select logic spans 16-24 address lines. With 36 user I/O pins and 15ns tPD matching 66.6MHz system clocks, the device provides 6-8 chip-select outputs with combinational propagation under one clock cycle. Per Altera's Classic EPLD application notes, the EP910's sum-of-products architecture natively suits address-decoding equations, and the 5V supply matches vintage CPU VCC rails without level shifting.
Recommended
Bus Interface Logic Between Asynchronous Peripherals
The EP910ILC-15 bridges asynchronous peripherals (UARTs, parallel ports, FIFOs) to a main processor bus, implementing handshake sequencing, width conversion, and protocol adaptation in a single device. With 24 macrocells supporting complex state machines at 15ns tPD, the EP910 handles bus arbitration and timing constraints that previously required 2-3 PAL devices. The EPROM-based configuration retains the protocol state machine through power cycles, which is critical for industrial communication modules where boot-time reconfigurability is undesirable.
Recommended
State-Machine Control of Electromechanical Subsystems
The EP910ILC-15 drives industrial relay, solenoid, and stepper-motor sequencing where deterministic timing and zero standby power are mandatory. With 15ns tPD and 24 macrocells, the device implements 8-12 state transitions driving optoisolated outputs at 5V CMOS levels. The industrial -40C to +85C temperature range supports factory-floor deployments. Per the Altera Classic EPLD datasheet, the EP910's EPROM cell provides 20-year data retention - ideal for long-life industrial control systems with 15-25 year service requirements.
Recommended
ASIC Prototyping Verification Platform
The EP910ILC-15 serves as an early-stage verification platform for ASIC designs targeting the same gate count. With 450 usable gates mapped to 24 macrocells and 15ns tPD, engineers can validate logic synthesis output, JTAG boundary-scan chains, and timing closure assumptions before committing to silicon. The EPROM technology supports 100+ erase/reprogram cycles during iterative refinement. This pre-silicon validation reduces ASIC respin risk by surfacing functional bugs at hardware speed rather than in simulation.
Recommended
Legacy Aerospace & Defense Avionics Systems
The EP910ILC-15 supports long-life aerospace and defense platforms where the original Classic EPLD design is locked for the airframe's 25-30 year service life. Per Rochester Electronics' authorized long-life product program, EP910 family parts remain qualified for DO-254 design assurance level B/C avionics. The 5V supply tolerance, industrial temperature range, and EPROM non-volatility meet legacy avionics environmental specifications, while Rochester's certificate-of-conformance sourcing chain satisfies defense procurement traceability requirements.
Recommended
Recommended Products Summary
Engineering reference data for EP910ILC-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910ILC-12 | EP910ILC-25 | EP910IDC-15 | EP910DC-15 | EP910LC-30T |
|---|---|---|---|---|---|---|
| Package | 44-pin PLCC (J-lead) | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same (ceramic variant) | 44-pin PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Propagation Delay (tPD) | 15 ns | 12 ns | 25 ns | 15 ns | 15 ns | 30 ns |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Maximum Frequency | 66.6 MHz | 83.3 MHz | 40 MHz | 66.6 MHz | 66.6 MHz | 33.3 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Industrial (-40C to +85C) | Industrial | Industrial | Commercial (0C to +70C) | Commercial | Industrial |
| Memory Type | EPROM (UV-erasable) | EPROM | EPROM | EPROM | EPROM | EPROM |
| Lifecycle Status | NRND | NRND | NRND | NRND | Obsolete (Rochester stock only) | NRND |
Key Differentiators
- 15ns speed grade offers balanced cost and 66.6MHz performance (vs EP910ILC-12)
- Industrial temperature range covers factory floor deployments (vs EP910IDC-15)
- PLCC-44 package enables both socket prototyping and SMT production (vs EP910DC-15)
Design Notes
The EP910ILC-15 operates from a single 5V supply (VCC +/- 10%) and draws approximately 5-10mA quiescent plus dynamic current proportional to switching frequency. Decouple VCC with 0.1uF ceramic + 10uF tantalum placed within 1cm of the package to suppress transient switching noise. Multiple VCC and GND pins around the PLCC-44 package should each be decoupled separately - shared decoupling creates ground bounce that can corrupt JTAG communication during in-system programming.
The 44-pin PLCC package uses J-lead SMT terminations that require precise land pattern design per IPC-7351. Maintain 0.050 inch pad pitch and use a PLCC-44 socket (e.g. 3M 8444-21B1-RK-TP) for prototyping so the EPROM window can be exposed to UV eraser. For production, solder directly with a controlled reflow profile: peak 220C for 30 seconds maximum, with preheat ramp 2C/second to avoid thermal shock to the ceramic-windowed package.
Three common pitfalls when designing with the EP910ILC-15: (1) Do not exceed the 5V VCC absolute maximum - latchup will occur above 7V. (2) When reprogramming via JTAG, ensure the TCK clock does not exceed 1MHz or the EPROM cell state can be corrupted. (3) Note that PLCC-44 packages use pin-1 indicator on the top-left corner - reverse orientation will short VCC to GND through pin pairs and destroy the part. Always verify pin-1 with the dot marker before power-up.
Compliance Information
RoHS/REACH status not explicitly stated in the verified data for the EP910ILC-15 vintage PLCC-44 product. Rochester Electronics' long-life product program typically provides lead-free and RoHS compliance letters on request. The MIL-STD-883B qualified variant EP910DM883B is available for defense programs requiring MIL-spec screening.
