EP2C70F672C8N - 70K LE Cyclone II FPGA, 422 I/O, 672-FBGA | Intel
MPN: EP2C70F672C8N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $305.38 | $305.38 |
| 10 | $285.5 | $2,855.00 |
| 100 | $268.4 | $26,840.00 |
| 500 | $252.1 | $126,050.00 |
| 1,000 | $239.75 | $239,750.00 |
EP2C70F672C8N Overview
A Field Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that belongs to the broader family of digital semiconductor ICs and embedded programmable logic. Cyclone II sits in the hierarchy as: FPGA -> programmable logic -> logic IC -> integrated circuit -> semiconductor. Cyclone II FPGAs were designed as a low-cost, high-volume alternative to ASICs for parallel processing, glue logic, and custom digital signal paths in cost-sensitive embedded designs.
Key features include 1,152,000 bits of embedded memory (1152 Kbit / approximately 144 KB), up to 422 user I/Os, embedded 18x18 multipliers, and PLL-based clock management. The 672-FBGA package supports commercial operating temperature 0C to 85C (junction), with -C8 speed grade at 1.15V to 1.25V core supply. The device is lead-free (Pb-free) and RoHS compliant.
Cyclone II devices use a look-up-table (LUT)-based logic element with embedded RAM blocks (M4K) and DSP blocks. The EP2C70 is the largest density in the family. Its 90 nm process and low static/dynamic power make it suitable for cost-driven applications that previously required multiple CPLDs or a small ASIC. Configuration is typically via JTAG or a serial configuration device such as the EPCS family.
Typical applications include industrial motor control and factory automation, video processing and display bridging, telecom line cards and protocol bridging, automotive infotainment prototypes, and test & measurement instrumentation. The large logic and memory capacity also suits prototyping of ASIC designs before mask production.
When designing with the EP2C70, allocate sufficient PCB layers for the 672-ball FBGA escape and follow Intel's pin connection guidelines for unused/dual-purpose pins. Power sequencing between VCCINT (core) and VCCIO (I/O banks) must follow the Cyclone II datasheet recommendations to avoid I/O latch-up.
This page synthesizes distributor pricing, drop-in same-family variants, and PCB design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP2C70F672C8N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C70F672C8N (same form factor and footprint) — differing in Package, Speed Grade, RoHS Status, Process Technology, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2C70F672C7N
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP2C70F672C6N
✅ Drop-In✓ In Stock
$178.3 / Unit
View Datasheet →EP2C70F672I8N
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP2C70F672C8
✅ Drop-In✓ In Stock
$238.2 / Unit
View Datasheet →EP2C70F672C8KK
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP2C70F672C8N Maximum Ratings & Electrical Characteristics
| Series | Cyclone II |
| Family | Cyclone II EP2C70 |
| Logic Elements (LE) | 68,416 |
| Logic Array Blocks (LABs) | 4,276 |
| Total Memory Bits | 1,152,000 (1152 Kbit) |
| Maximum User I/O | 422 |
| Package | 672-FBGA (FBGA-672) |
| Mounting Type | Surface Mount |
| Process Technology | 90 nm CMOS |
| Core Voltage (VCCINT) | 1.15 V to 1.25 V |
| Speed Grade | C8 |
| Operating Temperature | 0C to 85C (Commercial) |
| Lead Free / RoHS | Yes / Compliant |
| Maximum Internal Frequency | 402.5 MHz |
| Configuration Interface | JTAG, Serial (EPCS) |
EP2C70F672C8N Pin Configuration
| Pin A1 | I/O Bank 1 — User I/O or special function (see Cyclone II pin table) |
| Pin A2 | I/O Bank 1 — User I/O or special function |
| Pin A3 | VCCIO1 — I/O bank 1 supply voltage |
| Pin A4 | I/O Bank 1 — User I/O or special function |
| Pin A5 | I/O Bank 1 — User I/O or special function |
| Pin B1 | I/O Bank 2 — User I/O or special function |
| Pin B2 | GND — Ground reference |
| Pin B3 | VCCINT — Core supply 1.2V |
| Pin B4 | I/O Bank 1 — User I/O or special function |
| Pin B5 | I/O Bank 2 — User I/O or special function |
| Pin C1 | I/O Bank 2 — User I/O or special function |
| Pin C2 | I/O Bank 2 — User I/O or special function |
| Pin C3 | VCCIO2 — I/O bank 2 supply voltage |
| Pin C4 | I/O Bank 2 — User I/O or special function |
| Pin C5 | I/O Bank 2 — User I/O or special function |
| Pin D1 | I/O Bank 3 — User I/O or special function |
| Pin D2 | GND — Ground reference |
| Pin D3 | VCCINT — Core supply 1.2V |
| Pin D4 | I/O Bank 3 — User I/O or special function |
| Pin D5 | I/O Bank 3 — User I/O or special function |
| Pin E1 | TCK — JTAG test clock (dedicated) |
| Pin E2 | TMS — JTAG test mode select (dedicated) |
| Pin E3 | VCCA — PLL analog supply 1.2V |
| Pin E4 | nCONFIG — Configuration control (dedicated, active low) |
| Pin E5 | MSEL0 — Configuration mode select (dedicated) |
| Pin F1 | TDI — JTAG test data in (dedicated) |
| Pin F2 | TDO — JTAG test data out (dedicated) |
| Pin F3 | GND — Ground reference |
| Pin F4 | MSEL1 — Configuration mode select (dedicated) |
| Pin F5 | DCLK — Configuration clock (dedicated) |
| Pin G1 | I/O Bank 4 — User I/O or special function |
| Pin G2 | I/O Bank 4 — User I/O or special function |
| Pin G3 | VCCIO4 — I/O bank 4 supply voltage |
| Pin G4 | I/O Bank 4 — User I/O or special function |
| Pin G5 | I/O Bank 4 — User I/O or special function |
| Pin H1 | I/O Bank 5 — User I/O or special function |
| Pin H2 | GND — Ground reference |
| Pin H3 | VCCINT — Core supply 1.2V |
| Pin H4 | I/O Bank 5 — User I/O or special function |
| Pin H5 | I/O Bank 5 — User I/O or special function |
| Pin J1 | I/O Bank 5 — User I/O or special function |
| Pin J2 | I/O Bank 5 — User I/O or special function |
| Pin J3 | VCCIO5 — I/O bank 5 supply voltage |
| Pin J4 | I/O Bank 5 — User I/O or special function |
| Pin J5 | I/O Bank 5 — User I/O or special function |
| Pin K1 | I/O Bank 6 — User I/O or special function |
| Pin K2 | GND — Ground reference |
| Pin K3 | VCCINT — Core supply 1.2V |
| Pin K4 | I/O Bank 6 — User I/O or special function |
| Pin K5 | I/O Bank 6 — User I/O or special function |
| Pin L1 | I/O Bank 6 — User I/O or special function |
| Pin L2 | I/O Bank 6 — User I/O or special function |
| Pin L3 | VCCIO6 — I/O bank 6 supply voltage |
| Pin L4 | I/O Bank 6 — User I/O or special function |
| Pin L5 | I/O Bank 6 — User I/O or special function |
| Pin M1 | I/O Bank 7 — User I/O or special function |
| Pin M2 | GND — Ground reference |
| Pin M3 | VCCINT — Core supply 1.2V |
| Pin M4 | I/O Bank 7 — User I/O or special function |
| Pin M5 | I/O Bank 7 — User I/O or special function |
| Pin N1 | I/O Bank 7 — User I/O or special function |
| Pin N2 | I/O Bank 7 — User I/O or special function |
| Pin N3 | VCCIO7 — I/O bank 7 supply voltage |
| Pin N4 | I/O Bank 7 — User I/O or special function |
| Pin N5 | I/O Bank 7 — User I/O or special function |
| Pin P1 | I/O Bank 8 — User I/O or special function |
| Pin P2 | GND — Ground reference |
| Pin P3 | VCCINT — Core supply 1.2V |
| Pin P4 | I/O Bank 8 — User I/O or special function |
| Pin P5 | I/O Bank 8 — User I/O or special function |
Typical Applications
EP2C70F672C8N is suitable for 6 applications: Industrial Motor Control, Video Processing & Display Bridging, Telecom Line Card & Protocol Bridging, ASIC Prototyping Platform, Test & Measurement Instrumentation, Automotive Infotainment Prototyping.
Industrial Motor Control
The EP2C70F672C8N's 68,416 logic elements and 422 user I/Os make it well-suited for multi-axis industrial motor control and factory automation. The device can implement 4 to 8 channels of PWM generation, encoder quadrature decoding, and field-oriented control (FOC) loops in parallel hardware without DSP intervention. Its embedded 18x18 multipliers accelerate Park/Clarke transforms and PI controller math, while the 1152 Kbit of M4K memory provides buffering for sensor data and control-loop setpoints. The 672-FBGA supports the wide I/O count needed for simultaneous drive of multiple motors with encoder feedback, status LEDs, and CAN/RS-485 communication. Industrial temperature variants (EP2C70F672I8N) are drop-in compatible for harsh-environment deployment.
Recommended
Video Processing & Display Bridging
The EP2C70F672C8N serves as a video format converter, scaler, or display bridge between incompatible interfaces (e.g., BT.656 to LVDS, MIPI to RGB). The 402.5 MHz internal frequency supports pixel clocks for 1080p60 video at 148.5 MHz, with timing margin for additional processing pipelines. The 1152 Kbit of embedded memory buffers line-rate video frames, while 422 user I/Os accommodate parallel RGB, LVDS pairs, and HDMI control signals. The 90 nm CMOS process keeps dynamic power low for continuous video operation. Designers typically pair this FPGA with external DDR SDRAM for frame buffering; the device's M4K blocks handle small FIFOs and lookup tables for color space conversion.
Recommended
Telecom Line Card & Protocol Bridging
In telecom infrastructure, the EP2C70F672C8N functions as a protocol bridge between TDM (T1/E1), packet (Ethernet), and backplane fabrics. Its large logic capacity implements multiple HDLC controllers, framer/deframer blocks, and Ethernet MAC interfaces simultaneously. The 422 user I/Os accommodate SERDES-less multi-channel TDM plus parallel bus interfaces to network processors. Cyclone II's low static current (versus later families) suits always-on telecom line cards where thermal budget is tight. Industrial-grade variants support outdoor cabinet temperatures. The 672-FBGA package also enables high pin density for line cards with many physical ports.
Recommended
ASIC Prototyping Platform
The EP2C70F672C8N is widely used to prototype ASIC designs before committing to mask production, owing to its 68,416 logic elements and 1152 Kbit embedded memory that emulate moderate-complexity ASICs. Multiple FPGAs can be ganged via LVDS cross-boards to prototype ASICs that exceed single-chip capacity. The 672-FBGA package exposes enough I/O to break out ASIC pad rings for real-world validation. Quartus II synthesis from ASIC RTL (Verilog/VHDL) is well-supported, and the FPGA's deterministic timing aids in validating the design before tape-out. This use case typically pairs the FPGA with external SRAM or DDR memory controllers emulating the target ASIC's memory subsystem.
Recommended
Test & Measurement Instrumentation
In test equipment such as logic analyzers, protocol exercisers, and ATE stimulus generators, the EP2C70F672C8N delivers 68K logic elements for parallel pattern generation, capture FIFOs, and timing generators. The 422 user I/Os map to multi-channel probe pods, while 1152 Kbit of embedded memory stores stimulus vectors and capture buffers. The 402.5 MHz internal frequency supports up to 400 MHz pattern rates. Industrial temperature variants suit production-floor ATE where ambient temperatures are uncontrolled. The 672-FBGA package is appropriate for PCI/PCIe plug-in cards used in modular instrumentation chassis.
Recommended
Automotive Infotainment Prototyping
Although Cyclone II is not AEC-Q100 qualified, the EP2C70F672C8N is frequently used for pre-production automotive infotainment prototypes, where large logic capacity accelerates development of media decoders, CAN/LIN gateways, and display controllers. The 672-FBGA's high I/O count supports simultaneous connection to multiple displays, audio codecs, and vehicle network buses. The 90 nm process provides acceptable power consumption for vehicle bench testing. Production designs typically migrate to AEC-Q100-qualified automotive FPGA families such as Cyclone IV GX automotive or Xilinx Spartan-6 Q1, but Cyclone II remains a productive pre-silicon development platform.
Recommended
Recommended Products Summary
Engineering reference data for EP2C70F672C8N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C70F672C7N | EP2C70F672C6N | EP2C70F672I8N | EP2C70F672C8 | EP2C70F672C8KK |
|---|---|---|---|---|---|---|
| Package | 672-FBGA | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 |
| LABs | 4,276 | 4,276 | 4,276 | 4,276 | 4,276 | 4,276 |
| Speed Grade | C8 | C7 (~10-15% slower) | C6 (~20-25% slower) | I8 (industrial temp, same speed as C8) | C8 (identical) | C8 (identical) |
| Operating Temperature | 0C to 85C (Commercial) | 0C to 85C (Commercial) | 0C to 85C (Commercial) | -40C to 100C (Industrial) | 0C to 85C (Commercial) | 0C to 85C (Commercial) |
| Embedded Memory | 1152 Kbit | 1152 Kbit | 1152 Kbit | 1152 Kbit | 1152 Kbit | 1152 Kbit |
| User I/O (max) | 422 | 422 | 422 | 422 | 422 | 422 |
| Lead-Free Suffix | N (lead-free) | N | N | N | no N suffix | KK (tray packing) |
Key Differentiators
- Highest-density member of the Cyclone II family at the 672-FBGA footprint (vs EP2C50F672C8N)
- Faster C8 speed grade option in the same 672-FBGA package (vs EP2C70F672C7N)
- Industrial temperature variant available on same footprint (vs EP2C70F672C8N)
Design Notes
The EP2C70F672C8N requires VCCINT (1.15-1.25V, nominal 1.2V), VCCIO banks at 1.5/1.8/2.5/3.3V per bank, and VCCA (PLL analog 1.2V). Power sequencing is critical: VCCINT must ramp before or simultaneously with VCCIO to prevent I/O latch-up. Use a dedicated power supervisor (e.g., TPS3808) for proper sequencing. Decouple each VCCINT/VCCIO ball with 0.1uF and 10uF capacitors placed within 100 mils of the ball. VCCA must be filtered through a ferrite bead from VCCINT to prevent PLL jitter.
The 672-FBGA package requires a minimum of 4 PCB layers with continuous ground planes underneath for return-current paths. BGA escape routing typically uses 4-mil trace/space on inner layers and microvias on outer layers. Follow Intel's Cyclone II pin connection guidelines to handle unused/dual-purpose pins (tie to defined logic levels, never float). All JTAG pins (TCK/TMS/TDI/TDO) must be pulled to defined states during configuration to prevent spurious boundary-scan events.
Common pitfalls with the EP2C70F672C8N include: (1) failing to connect MSEL pins to the correct logic levels for the desired configuration mode (AS/PS/JTAG); (2) leaving dual-purpose I/O pins floating during configuration, which can cause unexpected behavior; (3) using 3.3V VCCIO on banks that interface to 1.8V peripherals without level translation; (4) ignoring the configuration CRC and not enabling the built-in CRC check (CRESET_N); (5) assuming C8 speed grade achieves datasheet Fmax without timing margin - always run Quartus II TimeQuest with realistic constraints.
Although FPGAs do not dissipate as much power as microprocessors, the EP2C70F672C8N can draw 1-3W typical and up to 5W at full utilization (100% LE toggle, all I/O switching). The 672-FBGA thermal resistance theta_JA is approximately 15 C/W with proper PCB thermal design (thermal vias under the BGA, internal copper planes). For enclosed industrial enclosures, estimate junction temperature rise: TJ = TA + (P x theta_JA). If TJ exceeds 100C for commercial grade or 125C for industrial grade, consider reducing toggle rate or adding airflow.
Place configuration flash (EPCS4/EPCS16/EPCS64) within 2 inches of the FPGA DATA/DCLK/nCONFIG/nCS pins to avoid signal-integrity issues. Match trace lengths within 100 mils for DCLK and DATA to prevent setup/hold violations at configuration time. Route JTAG signals TCK/TMS/TDI/TDO as a daisy-chain through all JTAG devices on the board, with 10K pull-ups on TCK/TMS/TDI and a 10K pull-down on TDO. Add a JTAG header accessible from the board edge for in-system programming.
Compliance Information
RoHS compliant and lead-free per 'N' suffix. Not AEC-Q100 qualified - Cyclone II is commercial/industrial grade. For automotive AEC-Q100 designs, use Cyclone IV GX automotive or Cyclone V automotive families instead.
