EPC1LC20HEC - 1Mb FPGA Config PROM, 20-PLCC | Intel (Altera)
MPN: EPC1LC20HEC β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.6 | $9,600.00 |
EPC1LC20HEC Overview
Background knowledge: a configuration PROM (programmable read-only memory) is a non-volatile memory device that holds the FPGA bitstream and serially shifts it into the SRAM configuration cells of the FPGA at every power-up, system reset, or reconfiguration event. Because SRAM-based FPGAs lose their configuration when power is removed, an external configuration PROM is required in most standalone designs. In the system hierarchy, a configuration PROM sits below the FPGA in the boot chain and is itself a type of serial configuration memory, which is a subcategory of non-volatile memory ICs.
Key features include a simple four-pin serial interface (nCS, DCLK, DATA, nINIT_CONF), daisy-chain capability for multi-device configuration, and a programmable nINIT_CONF pin that can drive the FPGA nCONFIG or nSTATUS lines. The "HEC" suffix denotes the higher-temperature variant rated for the commercial 0C to +70C range and ships in tube packaging. Internal oscillator-free design means timing is fully FPGA-driven via the DCLK line.
The device architecture combines a one-time-programmable serial EEPROM array with a serial interface state machine and a dedicated DONE pin for chain completion signalling. The 1-Mbit density comfortably holds the largest Altera APEX and Cyclone configuration files with margin, and the 20-pin PLCC socket allows easy in-system programming during prototyping and field upgrades using Altera's free software.
Typical applications include boot configuration for legacy APEX 20K and ACEX 1K FPGAs, factory programming stations, and any Altera/Intel FPGA design that previously relied on the discontinued EPC1 or EPC2 devices. The EPC1LC20 is widely used in industrial control cards, telecommunications line cards, and military-aerospace retrofits where Altera's older device families remain in service.
Designers should note that the EPC1LC20 is not supported by newer Altera/Intel FPGA families (Cyclone III and beyond), which use the EPCS or EPCQ serial flash devices instead. Verify FPGA-configuration-PROM compatibility before selection, and use a 20-pin PLCC socket for in-circuit reprogramming.
Drop-in alternatives for EPC1LC20HEC β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1LC20HEC (same form factor and footprint) β differing in Memory Type, Mounting Type, Package, Compatible FPGA Families, Supply Voltage.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC1LC20
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEPC2LC20
β Drop-Inβ In Stock
$7.2 / Unit
View Datasheet βEPC1LC20HEC Maximum Ratings & Electrical Characteristics
| Memory Type | OTP Configuration PROM (EEPROM-based) |
| Memory Density | 1 Mbit (1,048,576 bits) |
| Interface | Serial (4-wire: nCS, DCLK, DATA, nINIT_CONF) |
| Max Configuration Clock | 8 MHz |
| Supply Voltage | 3.3 V or 5 V |
| Programmability | One-Time Programmable (OTP) |
| Package | 20-pin PLCC (J-lead, 9x9 mm) |
| Operating Temperature | 0C to +70C (commercial) |
| Daisy Chain Support | Yes |
| nINIT_CONF Pin | Yes (programmable as nCONFIG or nSTATUS) |
| DONE Pin | Yes |
| Compatible FPGA Families | APEX, ACEX, FLEX, Cyclone (legacy) |
| Mounting Type | Surface Mount (PLCC socket recommended) |
EPC1LC20HEC Pin Configuration
| Pin 1 | nCS β Chip select (active low) |
| Pin 2 | DATA β Serial data output to FPGA |
| Pin 3 | DCLK β Configuration clock input from FPGA |
| Pin 4 | nINIT_CONF β Initiate configuration (programmable as nCONFIG or nSTATUS) |
| Pin 5 | VCC β Supply voltage (3.3 V or 5 V) |
| Pin 6 | NC β Not connected (per datasheet) |
| Pin 7 | OE β Output enable |
| Pin 8 | nCASC β Cascade output (for daisy chain) |
| Pin 9 | DONE β Configuration complete output |
| Pin 10 | GND β Ground |
| Pin 11 | NC β Not connected (per datasheet) |
| Pin 12 | NC β Not connected (per datasheet) |
| Pin 13 | NC β Not connected (per datasheet) |
| Pin 14 | NC β Not connected (per datasheet) |
| Pin 15 | NC β Not connected (per datasheet) |
| Pin 16 | NC β Not connected (per datasheet) |
| Pin 17 | NC β Not connected (per datasheet) |
| Pin 18 | NC β Not connected (per datasheet) |
| Pin 19 | NC β Not connected (per datasheet) |
| Pin 20 | GND β Ground |
Typical Applications
EPC1LC20HEC is suitable for 6 applications: APEX 20K FPGA Boot Configuration, Cyclone FPGA Legacy Boot Configuration, Factory Programming Station, Industrial Control Card, Telecommunications Line Card, Military/Aerospace Retrofit.
APEX 20K FPGA Boot Configuration
The EPC1LC20HEC stores and serially shifts the 1-Mbit configuration bitstream into Altera APEX 20K FPGAs at every power-up, replacing the need for parallel EPROM boot storage. The four-wire serial interface (nCS, DCLK, DATA, nINIT_CONF) and 8 MHz max configuration clock keep boot times under 150 ms for the largest APEX bitstreams. Placed adjacent to the FPGA in a 20-pin PLCC socket for easy field reprogramming, the HEC's 1 Mbit density covers most APEX 20K100 / 20K200 designs; for larger APEX 20K400/600/1000 designs, step up to the pin-compatible EPC2LC20 (2 Mbit). Unlike parallel EPROM boot, the EPC1LC20HEC needs no address/data bus, freeing FPGA I/O for application use.
Recommended
Cyclone FPGA Legacy Boot Configuration
The EPC1LC20HEC supports the original Cyclone (EP1C3, EP1C6, EP1C12, EP1C20) FPGAs in passive-serial (PS) configuration mode using DCLK from the FPGA, nCS, DATA, and the nINIT_CONF pin that drives nCONFIG/nSTATUS. The 1-Mbit density fits smaller Cyclone designs; for the Cyclone EP1C20 with bitstreams exceeding 1 Mbit, the EPC2LC20 is the same-footprint upgrade. Placed on a 20-pin PLCC socket near the FPGA's CONF_DONE and nSTATUS pins, the EPC1LC20HEC eliminates the need for an external configuration oscillator. Trade-off: legacy Cyclone designs can also use the newer EPCS1 serial flash, but that requires an SOIC footprint and Quartus programming changes, whereas the EPC1LC20HEC preserves the original PLCC-20 PCB.
Recommended
Factory Programming Station
The EPC1LC20HEC's one-time-programmable (OTP) array makes it a reliable, low-cost storage medium for factory programming stations that pre-load FPGA bitstreams before board assembly. Programming is performed via Altera's free software through the JTAG or PS programming interface; once written, the configuration data is permanent and immune to corruption. Placed in a 20-pin PLCC socket on the programming jig, the EPC1LC20HEC allows rapid device swap and in-line verification. Its 0C to +70C commercial temperature range is well-suited for production environments. Trade-off: OTP prevents in-system firmware updates, so production planning must lock the bitstream before programming.
Recommended
Industrial Control Card
The EPC1LC20HEC serves as the configuration memory for Altera FPGAs on industrial control cards that drive motor control, PLC logic, and process automation subsystems. The 3.3 V or 5 V supply flexibility matches the legacy voltage rails common on industrial PLC backplanes, and the 20-pin PLCC socket allows field service technicians to swap pre-programmed PROMs when upgrading firmware across machine variants. With a 1 Mbit density and 8 MHz configuration clock, cold-start boot time stays under 100 ms, which is critical for safety-rated controllers that must complete initialization within PLC scan cycles. Trade-off: the obsolete lifecycle status means future industrial designs should evaluate EPCS or EPCQ serial flash.
Recommended
Telecommunications Line Card
The EPC1LC20HEC configures Altera APEX 20K and ACEX 1K FPGAs that implement telecom line-interface functions such as T1/E1 framers, HDLC controllers, and ATM segmentation/reassembly blocks. The 20-pin PLCC package with socket allows field replacement in central-office equipment where PROM-swap is a standard maintenance procedure, while the HEC's commercial 0C to +70C temperature range suits temperature-controlled central-office environments. Daisy-chaining via the nCS and DATA pins lets two EPC1LC20HEC devices together deliver 2 Mbit for larger APEX 20K bitstreams on a single serial chain. Trade-off: legacy telecom designs must monitor EPC1LC20HEC inventory carefully given the obsolete lifecycle.
Recommended
Military/Aerospace Retrofit
The EPC1LC20HEC is widely specified in military and aerospace retrofit programs that maintain legacy Altera FPGAs (APEX, ACEX, FLEX 10K) on fielded systems, because the 20-pin PLCC socket enables field-replaceable module maintenance under MIL-STD-454 and MIL-HDBK-454 guidelines. Its 1 Mbit OTP density, 3.3 V/5 V dual-supply support, and Altera-datasheet-claimed 8 MHz configuration clock provide reliable boot for radar signal processing, avionics databus, and electronic-warfare subsystems. For higher-grade temperature screening, the EPC1 family also offers industrial (-40C to +85C) variants on the same PLCC-20 footprint. Trade-off: obsolete lifecycle and military-grade (MIL-PRF-38535) compliance must be verified part-by-part with the supplier.
Recommended
Recommended Products Summary
Engineering reference data for EPC1LC20HEC β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1LC20 | EPC2LC20 | EPC1PC8 |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | 20-pin PLCC | 20-pin PLCC - same | 20-pin PLCC - same | 8-pin PDIP - different |
| Memory Density | 1 Mbit | 1 Mbit | 2 Mbit | 1 Mbit |
| Max Config Clock | 8 MHz | 8 MHz | 8 MHz | 8 MHz |
| Supply Voltage | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
| Programmability | OTP (one-time programmable) | OTP | OTP | OTP |
| Daisy Chain Support | Yes | Yes | Yes | Yes |
Key Differentiators
- Higher bitstream capacity upgrade path (vs EPC1LC20 (base))
- Socket-friendly surface-mount package (vs EPC1PC8 (PDIP))
- Daisy-chainable for >1 Mbit streams (vs Single-PROM designs)
Design Notes
Place the EPC1LC20HEC as close as possible to the Altera FPGA's configuration pins (nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA0) and route the serial DATA trace as a 50-ohm controlled-impedance microstrip to avoid ringing at 8 MHz. Use a 20-pin PLCC socket (Yamaichi or 3M) instead of soldering the EPC1LC20HEC directly, so field replacement and factory programming are possible without board rework.
Do not use the EPC1LC20HEC with Cyclone III / Cyclone IV / newer FPGA families - those use EPCS or EPCQ serial flash with the active-serial (AS) interface, not the legacy passive-serial (PS) interface of the EPC1 family. According to the Altera Configuration Devices Handbook, attempting to program an EPC1LC20HEC with a Quartus bitstream targeted at AS-mode flash will fail. Verify FPGA-configuration-PROM compatibility in the Quartus device selection before ordering.
Add a 0.1 uF decoupling capacitor directly between VCC (pin 5) and GND (pin 10/20) of the EPC1LC20HEC, plus a 10 uF bulk capacitor on the same supply rail. The PROM draws short current spikes during the serial clock edges, and inadequate decoupling can corrupt the DATA output or stall the configuration chain at power-up. Keep the DCLK trace shorter than 50 mm to prevent signal-integrity issues at the 8 MHz maximum clock rate.
Compliance Information
Compliance status not present in the Verified Web Data. EPC1LC20HEC is obsolete and last shipped in legacy Altera packaging; RoHS / REACH compliance must be verified with the franchised distributor per date-code.
