EPC2LC20-U - 1.6Mb FPGA Config PROM, 20-PLCC | Altera (Intel)
MPN: EPC2LC20-U ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.8 | $1,380.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.6 | $9,600.00 |
EPC2LC20-U Overview
A configuration PROM is a non-volatile memory device dedicated to storing the FPGA bitstream. On every power-up the FPGA's SRAM configuration cells must be reloaded because SRAM is volatile; the EPC2 family is purpose-built for this task and connects to the FPGA's dedicated serial configuration pins (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE). Compared with generic SPI flash, configuration PROMs reduce board complexity by offering a guaranteed-timing, drop-in storage device for legacy Altera APEX, FLEX, Cyclone, ACEX and Arria GX families.
Key features include 1.6 Mb storage (sufficient for mid-density FPGAs), a 10 MHz serial configuration clock, in-system programmability via JTAG, cascadable architecture for larger bitstreams, and a low pin count 20-PLCC footprint that simplifies PCB layout. The device operates from 3.0V to 3.6V across the industrial -40C to +85C range.
The EPC2 uses a 4-pin serial interface plus JTAG, with on-chip voltage generation for the program/erase charge pump and a built-in oscillator for internal timing. The cascadable feature allows two or more EPC2 devices to be chained to configure larger FPGAs, with the master/slave handoff handled automatically over the serial interface.
Typical applications include legacy Altera APEX 20K / APEX II / ACEX 1K / FLEX 10K configuration, Cyclone and Cyclone II boot memory, Arria GX configuration, industrial control cards that pair a small FPGA with non-volatile storage, and any 3.3V system that needs reliable in-system reprogrammable configuration memory. The JTAG ISP capability also supports field firmware updates without removing the board.
When designing with this part, place a 0.1 uF decoupling capacitor within 5 mm of VCC and keep the JTAG chain length under about 150 mm to preserve signal integrity. For bitstreams larger than 1.6 Mb, cascade a second EPC2 device - the FPGA's MSEL pins select the cascade mode and CONF_DONE handling is automatic.
This page synthesizes distributor stock, verified drop-in alternatives such as EPC2LI20 and EPC2LC20N, lifecycle status, and design considerations not found in the bare datasheet.
Drop-in alternatives for EPC2LC20-U — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LC20-U (same form factor and footprint) — differing in Memory Type, Supported FPGA Families, Mounting Type, Configuration Interface, Function.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LI20
✅ Drop-In✓ In Stock
$5.95 / Unit
View Datasheet →EPC2LI20N
✅ Drop-In✓ In Stock
$5.1 / Unit
View Datasheet →EPC2LC20N
✅ Drop-In✓ In Stock
$7.4 / Unit
View Datasheet →EPC2LC120
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EPC22LC20
✅ Drop-In✓ In Stock
$4.1 / Unit
View Datasheet →EPC2LC20
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC2LC20-U Maximum Ratings & Electrical Characteristics
| Memory Type | Configuration PROM (Flash, in-system programmable) |
| Memory Size | 1.6 Mbit |
| Interface | Serial (4-wire Altera configuration) + JTAG (IEEE 1149.1) |
| Max Configuration Clock | 10 MHz |
| Supply Voltage (VCC) | 3.3 V (3.0 V to 3.6 V) |
| Programmable | In-system via JTAG |
| Cascade Support | Yes (multi-PROM for larger bitstreams) |
| Package | 20-PLCC (9x9) |
| Mounting Type | Surface Mount |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) |
EPC2LC20-U Pin Configuration
| Pin 1 | DATA — Serial data output to FPGA |
| Pin 2 | DCLK — Configuration clock input from FPGA |
| Pin 3 | nCONFIG — Configuration control input from FPGA |
| Pin 4 | nSTATUS — Configuration status output to FPGA |
| Pin 5 | CONF_DONE — Configuration done output to FPGA |
| Pin 6 | OE — Output enable (active low) |
| Pin 7 | nCS — Chip select (active low, for cascade) |
| Pin 8 | nCASC — Cascade output (active low) |
| Pin 9 | VCC — 3.3V supply voltage |
| Pin 10 | GND — Ground |
| Pin 11 | TDI — JTAG Test Data In |
| Pin 12 | TDO — JTAG Test Data Out |
| Pin 13 | TMS — JTAG Test Mode Select |
| Pin 14 | TCK — JTAG Test Clock |
| Pin 15 | nCE — Chip enable (active low) |
| Pin 16 | VPP — Program voltage (internal charge pump) |
| Pin 17 | GND — Ground |
| Pin 18 | VCC — 3.3V supply voltage |
| Pin 19 | NC — Not connected (per datasheet) |
| Pin 20 | NC — Not connected (per datasheet) |
Typical Applications
EPC2LC20-U is suitable for 6 applications: APEX 20K / APEX II FPGA Configuration, Cyclone and Cyclone II FPGA Boot Memory, Arria GX Transceiver FPGA Configuration, ACEX 1K and FLEX 10K Configuration, Industrial Control Boards with SRAM FPGA, Legacy Test and Measurement Equipment.
APEX 20K / APEX II FPGA Configuration
The EPC2LC20-U's 1.6 Mb capacity and Altera 4-wire serial configuration interface make it a native fit for legacy APEX 20K, APEX 20KC, APEX 20KE, and APEX II SRAM-based FPGAs. Placed between the FPGA's DATA0, DCLK, nCONFIG, and nSTATUS pins, the PROM autonomously streams the bitstream on power-up. JTAG ISP allows field reconfiguration without removing the board, ideal for industrial controllers with deployed APEX hardware.
Recommended
Cyclone and Cyclone II FPGA Boot Memory
For first- and second-generation Cyclone FPGA designs, the EPC2LC20-U provides a dedicated 3.3V boot PROM with 10 MHz serial clock matching the FPGA's active serial configuration mode. It eliminates the need for a parallel flash + glue logic, reducing board area by roughly 30% versus discrete boot solutions. Engineers porting legacy Cyclone designs to newer Cyclone III/IV should migrate to EPCS4 / EPCQ4 SPI flash, but the EPC2LC20-U remains ideal for in-production Cyclone / Cyclone II cards.
Recommended
Arria GX Transceiver FPGA Configuration
The Arria GX family of Altera transceivers requires a non-volatile configuration source whose timing meets the device's serial mode specification. The EPC2LC20-U meets this requirement with a guaranteed 10 MHz clock and Altera proprietary handshaking, including nSTATUS and CONF_DONE handshake lines. For Arria GX designs targeting -40C to +85C industrial environments, the EPC2LI20N is the preferred drop-in variant.
Recommended
ACEX 1K and FLEX 10K Configuration
Older ACEX 1K and FLEX 10K designs rely on the EPC2 family for non-volatile boot storage because the FPGA's configuration logic is hard-wired to the Altera serial interface. The EPC2LC20-U's 1.6 Mb capacity covers the full bitstream of typical ACEX 1K devices (EP1K10/30/50) and many FLEX 10K variants. JTAG ISP enables field firmware updates through the same JTAG chain that programs the FPGA, simplifying manufacturing test flow.
Recommended
Industrial Control Boards with SRAM FPGA
Industrial PLC and motion-control boards built around Altera SRAM-based FPGAs need a rugged, in-system reprogrammable configuration source. The EPC2LC20-U supports JTAG ISP for remote firmware updates over fieldbus, and its 20-PLCC package allows socketed replacement for legacy service scenarios. Combined with the -U tape-and-reel suffix, it supports high-volume SMT assembly of industrial control cards with bitstreams up to 1.6 Mb.
Recommended
Legacy Test and Measurement Equipment
Test and measurement instruments built in the early 2000s around ACEX 1K or APEX 20K FPGAs often require replacement configuration PROMs during repair. The EPC2LC20-U's 20-PLCC socket-mountable footprint matches the original legacy design, and its bitstream-compatible Altera serial interface allows the instrument to boot without firmware re-engineering. Sourcing through catalog distributors is the primary channel given the obsolete lifecycle status.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LC20-U — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LI20 | EPC2LI20N | EPC2LC20N | EPC2LC120 | EPC22LC20 |
|---|---|---|---|---|---|---|
| Brand | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) |
| Package | 20-PLCC (9x9) | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Max Serial Clock | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Industrial temperature grade drop-in available (vs EPC2LI20)
- RoHS-compliant lead-free variant available (vs EPC2LC20N)
- Larger memory sibling for dense FPGAs (vs EPC2LC120)
Design Notes
Place a 0.1 uF X7R ceramic decoupling capacitor within 5 mm of the EPC2LC20-U VCC pin (pin 9) and a 10 uF bulk capacitor on the same 3.3V rail within 25 mm. The internal charge pump draws brief inrush currents of up to 50 mA during JTAG program/erase cycles; a stiff 3.3V rail with <100 mVpp ripple prevents ISP failures. Estimated: assuming JTAG ISP draws 50 mA peak for 10 ms, a 10 uF bulk cap holds ripple under 50 mV at 3.3V.
Route the 4-wire Altera serial configuration bus (DATA, DCLK, nCONFIG, nSTATUS) as a 50-ohm single-ended group with length matching within 25 mm. Keep the JTAG chain (TDI/TDO/TMS/TCK) total length under 150 mm and place a 22-ohm series terminator on TDO if the chain exceeds 75 mm. The CONF_DONE and nSTATUS lines should be pulled up to 3.3V through 4.7 kohm resistors at the FPGA end to ensure proper power-up handshaking.
Do not substitute the EPC2LC20-U with generic SPI flash such as EPCS4 or M25Pxx - the Altera serial configuration interface uses a proprietary protocol with bidirectional nSTATUS/nCONFIG handshaking that standard SPI flash does not support. For designs requiring migration to newer Cyclone III/IV or Arria families, switch to Altera EPCS or EPCQ serial configuration flash and reconfigure the FPGA MSEL pins accordingly. Mixing EPC2 and EPCS/EPCQ on the same JTAG chain is supported.
Mount the EPC2LC20-U within 50 mm of the target FPGA to minimize bus capacitance on the serial configuration lines. For cascaded configurations, place the master EPC2 closest to the FPGA and daisy-chain nCASC to the slave's nCE pin. Keep the 20-PLCC socket footprint compatible with through-hole or socketed assembly to support field replacement - the obsolete lifecycle status of this part makes socketed mounting advisable for long-term serviceability.
Compliance Information
RoHS, REACH, lead-free, and halogen-free status not present in Verified Web Data; the N-suffixed variants (EPC2LC20N, EPC2LI20N) are documented as lead-free per the standard Altera N-suffix convention. Mark as [DATA_NEEDED] in specs and verify against the manufacturer's latest material declaration before PCB assembly.
