Intel

EPF6010ATC144-3 - 10K Gates FLEX 6000 FPGA, 144-TQFP | Intel

Name: EPF6010ATC144-3 - 10K Gates FLEX 6000 FPGA, 144-TQFP | Intel
Brand: Intel
SKU: EPF6010ATC144-3
Price: 9.75 USD
Availability: InStock

MPN: EPF6010ATC144-3 ✗ End of Life

In Stock Ships in 1-3 business days

3.0 V to 3.6 V Vdss LVTTL, LVCMOS, PCI compatible; multiVolt I/O Rds(on) 144-pin TQFP (Fine Line) Package 142.86 MHz Speed SRAM (volatile, re-programmable) Memory

From $9.75 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$18.5	$18.50
10	$16.2	$162.00
100	$13.85	$1,385.00
500	$11.4	$5,700.00
1,000	$9.75	$9,750.00

ℹ️ All prices are in USD

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EPF6010ATC144-3 Overview

The Intel (formerly Altera) EPF6010ATC144-3 is a 10,000-gate FLEX 6000 family Field-Programmable Gate Array (FPGA) housed in a 144-pin Thin Quad Flat Pack (TQFP) package. Built on a 0.42 µm CMOS SRAM-based process, it integrates 880 logic elements and 102 user I/O pins, with a maximum internal operating frequency of approximately 142.86 MHz and a 3.3 V single supply requirement.

A Field-Programmable Gate Array (FPGA) is a type of programmable logic device that combines the density of gate arrays with the design flexibility of user-customizable interconnect. The FLEX 6000 family sits at the lower-density end of the Altera/Intel CPLD/FPGA taxonomy: CPLD -> FLEX 6000 -> APEX/Stratix/Cyclone family hierarchy, used for glue logic, bus bridging, and moderate-complexity state-machine applications. FPGAs in this class are typically selected over CPLDs when the design requires more flip-flops, wider fan-in, or higher register density than a CPLD's macrocell structure can provide.

Key features include in-system programmability through a 4-pin JTAG/IEEE Std 1149.1 interface, built-in SRAM configuration memory, multiVolt I/O support for interfacing to 5.0 V, 3.3 V, and 2.5 V devices, and built-in boundary-scan test (BST) circuitry. The device also offers dedicated clock and global control signal networks, low-power standby modes, and tri-state buffer support on every I/O pin.

From an architectural standpoint, the EPF6010ATC144-3 uses logic elements (LEs) — each containing a 4-input look-up table, a programmable flip-flop, and dedicated carry/cascade chains — wired through a continuous, row-and-column FastTrack interconnect. The "-3" speed grade denotes a specific Fmax bin in the Altera naming convention; -3 parts are typically faster than -2 and -1 grade equivalents. Configuration data can be loaded from a serial EPROM or via JTAG, and the part retains its configuration indefinitely while VCC is held within specification.

Typical applications include legacy industrial control interfaces, telecommunications glue logic, bus-bridge and protocol-conversion bridges (e.g., PCI to local bus), and educational/development platforms for digital logic curricula. The wide 3.3 V supply tolerance makes it compatible with both 3.3 V and 5 V mixed-voltage systems when used with proper level-shifting.

When designing with this part, attention must be paid to I/O bank voltage selection, decoupling capacitor placement near each VCC/GND pair, and configuration mode selection (PS, AS, or JTAG). The 144-pin TQFP is a fine-pitch (0.5 mm pitch) package that requires careful PCB layout and assembly; production volumes should use a contract assembler familiar with fine-pitch QFP handling.

Drop-in alternatives for EPF6010ATC144-3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF6010ATC144-3 (same form factor and footprint) — differing in Package, Configuration Method, Process Technology, Logic Array Blocks (LABs), Speed Grade.

EPF6010ATC144-1

Intel

Package: 144-LQFP / TQFP-144 (20x20 mm)

Configuration Method: SRAM, in-system programmable via ByteBlaster/BitBlaster

Process Technology: 0.42 µm CMOS