EP20K600CF672I9 - APEX 20KC FPGA 600K Gates 672-FBGA | Intel
MPN: EP20K600CF672I9 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $255 | $2,550.00 |
| 100 | $215 | $21,500.00 |
| 500 | $178 | $89,000.00 |
| 1,000 | $152 | $152,000.00 |
EP20K600CF672I9 Overview
An FPGA (Field-Programmable Gate Array) is a programmable logic device that lets designers implement custom digital circuits in silicon without the cost of an ASIC mask set. Within the programmable logic hierarchy, FPGAs sit above CPLDs in logic density and below ASICs in per-unit cost at high volume; the APEX 20KC family specifically combines Look-Up Table (LUT) based logic fabric with embedded MultiTrack interconnect and dual-port RAM blocks, occupying the high-density segment alongside contemporaries such as the Xilinx Virtex-II family.
The EP20K600CF672I9 features embedded array blocks (EABs) for memory and DSP functions, dedicated clock management circuitry with up to four phase-locked loops (PLLs), and supports a wide range of I/O standards including LVTTL, LVCMOS, PCI, and LVDS. Its 24,320 logic cells combined with up to 311 user I/O pins provide significant routing flexibility, while the FC-FBGA package minimizes board area for space-constrained applications. The 0.15 µm process enables 250 MHz internal performance while keeping power consumption manageable.
Typical applications include telecommunications switching fabric, network routers, high-speed serial protocol bridging, video processing pipelines, and industrial automation controllers. Designers value the APEX 20KC family for its multi-level memory hierarchy (distributed RAM + EABs), predictable timing closure via TimeQuest-style static timing analysis, and mature Quartus development toolchain. Industrial temperature grading extends applicability into harsh-environment deployments such as factory automation and outdoor telecommunications equipment.
When designing with this device, allocate sufficient PCB layers for power distribution and signal integrity - the 672-ball BGA requires careful escape routing on a minimum 4-layer stack-up. Decoupling must follow the manufacturer reference design: multiple bulk and high-frequency ceramic capacitors near each power pin pair. Leave firmware reconfigurable via JTAG for in-field updates, and follow the Altera/Intel configuration guidelines for passive serial or JTAG programming modes.
This page synthesizes distributor stock levels, drop-in same-package alternatives, current pricing tiers, and design considerations that complement the manufacturer datasheet - information typically not consolidated in a single source for obsolete or hard-to-find programmable logic devices.
Drop-in alternatives for EP20K600CF672I9 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600CF672I9 (same form factor and footprint) — differing in Operating Temperature, Process Technology, Configuration Interface, Package, Package Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600CF672I8
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP20K600CF672I7
✅ Drop-In✓ In Stock
$220 / Unit
View Datasheet →EP20K600CF672C9
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K600CF672C8
✅ Drop-In✓ In Stock
$322.4109 / Unit
View Datasheet →EP20K600CF672C7
✅ Drop-In✓ In Stock
$2267.89 / Unit
View Datasheet →EP20K600CF672I9 Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Logic Elements / Cells | 24,320 |
| System Gates | 600,000 |
| Maximum Operating Frequency | 250 MHz |
| Process Technology | 0.15 µm CMOS |
| Core Voltage | 1.8 V |
| Package | 672-pin FC-FBGA |
| Mounting Type | Surface Mount (BGA) |
| Temperature Grade | Industrial (-40°C to +85°C) |
| Speed Grade | 9 (fastest bin) |
| User I/O Pins | 311 (max) |
| PLLs | Up to 4 |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS |
| Configuration Mode | Passive Serial / JTAG |
| Maximum Seated Height | 2.1 mm |
EP20K600CF672I9 672-pin fc-fbga Pin Configuration Guide
Pin configuration for EP20K600CF672I9 (672-pin fc-fbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K600CF672I9.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K600CF672I9 is suitable for 6 applications: Telecommunications Switching Fabric, Network Router and Switch Datapath, Video Processing Pipelines, Industrial Automation Controllers, Legacy Test and Measurement Equipment, Medical Imaging Pre-Processing.
Telecommunications Switching Fabric
The EP20K600CF672I9's 600K system gates, 311 user I/Os, and 250 MHz internal performance make it well-suited for telecommunications switching fabrics. The APEX 20KC family's embedded array blocks (EABs) and dual-port RAM blocks enable efficient implementation of cell/frame buffers, while the LVDS I/O support allows direct connection to high-speed serial backplanes. At 1.8 V core, the device fits 24,320 logic elements into a moderately compact power envelope, and the industrial temperature grading supports outdoor cabinet deployments such as DSLAM and central-office line-card slots.
Recommended
Network Router and Switch Datapath
The EP20K600CF672I9 is an established choice for network router and switch datapath designs, where 24,320 logic elements provide ample room for packet classification engines, queue managers, and serializer/deserializer glue logic. The 672-ball FC-FBGA package exposes sufficient I/O for multi-port Gigabit Ethernet or POS-PHY interfaces, and the four integrated PLLs generate the multiple clock domains typically required in switched-fabric designs. Quartus II Place-and-Route provides the static timing analysis needed for closed timing on 250 MHz datapaths.
Recommended
Video Processing Pipelines
With 24,320 logic elements and dual-port EAB-based memory blocks, the EP20K600CF672I9 supports video processing pipelines such as SD/HD video scaling, de-interlacing, and color-space conversion. The industrial temperature grading enables deployment in industrial video equipment and digital signage controllers. Designers typically implement line buffers in EABs and use the device's LVDS I/O to connect directly to video ADCs/DACs. The 0.15 µm process provides the headroom for 250 MHz pixel-clock pipelines that easily handle 1080p60 throughput.
Recommended
Industrial Automation Controllers
The EP20K600CF672I9 is well-suited for industrial automation controllers, where its 600K-gate density accommodates multiple fieldbus protocol bridges (Profibus, DeviceNet, CANopen) plus deterministic motion-control state machines. The -40°C to +85°C industrial temperature grading covers factory floor and outdoor cabinet deployments. The device's 1.8 V core and 672-ball BGA package allow compact controller board designs, while the legacy Quartus II toolchain (still supported for APEX 20KC) preserves software investment for long-lifecycle automation products.
Recommended
Legacy Test and Measurement Equipment
The EP20K600CF672I9 is a common component in legacy test and measurement equipment, where it implements arbitrary waveform generators, high-speed data acquisition sequencers, and custom protocol analyzers. Its large logic capacity accommodates deep pattern-matching state machines, while the EAB-based RAM enables real-time sample buffering. Engineers maintaining these instruments need drop-in same-package replacements when refurbishing units; the EP20K600CF672I8 and EP20K600CF672I7 provide such options with identical PCB footprints and minor speed-bin differences.
Recommended
Medical Imaging Pre-Processing
The EP20K600CF672I9 is found in older medical imaging pre-processing subsystems such as ultrasound beamformers, MRI receiver-channel digitizers, and patient-monitoring DSP front-ends. Its industrial temperature grade and 24,320 logic elements enable ultrasound beamforming matrix multipliers implemented as parallel multiply-accumulate trees, while EAB-based buffers hold channel data between the analog front-end and downstream DSP. Designers building new medical devices should consider migrating to modern Intel Cyclone V or Xilinx Zynq-7000 families for active lifecycle support.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600CF672I9 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600CF672I8 | EP20K600CF672I7 | EP20K600CF672C9 | EP20K600CF672C8 | EP20K600CF672C7 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-pin FC-FBGA | 672-pin FC-FBGA (same) | 672-pin FC-FBGA (same) | 672-pin FC-FBGA (same) | 672-pin FC-FBGA (same) | 672-pin FC-FBGA (same) |
| Speed Grade | 9 (fastest) | 8 (~10% slower) | 7 (~20% slower) | 9 (same speed) | 8 (~10% slower) | 7 (~20% slower) |
| Temperature Grade | Industrial (-40°C to +85°C) | Industrial (same) | Industrial (same) | Commercial (0°C to +85°C) | Commercial | Commercial |
| System Gates | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 |
| Logic Elements | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Fastest speed bin in the APEX 20KC family (vs EP20K600CF672I8)
- Industrial temperature grading supports harsh environments (vs EP20K600CF672C9)
- Same-package drop-in simplifies board respins (vs Smaller EP20K400CF672I9 (different die))
Design Notes
The EP20K600CF672I9 uses a 672-ball Fine-pitch Chip-Scale BGA (FC-FBGA) with balls on a 1.0 mm pitch. A minimum 4-layer PCB stack-up is required for proper escape routing, with dedicated power and ground planes adjacent to the BGA footprint. Use microvia (laser-drilled) stack-up if 8-layer routing is preferred for signal integrity on high-speed LVDS pairs. Follow the Altera AN 114 (APEX 20KC PCB Layout Guidelines) for via-in-pad recommendations, ball pad diameter, and solder mask-defined vs non-solder-mask-defined pad decisions.
Decoupling must follow the APEX 20KC reference design: place 0.1 µF and 0.01 µF X7R ceramic capacitors within 100 mils of every VCCINT and VCCIO pin pair, plus 100 µF tantalum or polymer bulk capacitors on each power rail. Use multiple vias per decoupling pad to reduce inductance. The 1.8 V core (VCCINT) typically draws 500 mA to 2 A depending on logic utilization and toggle rate; budget a 3 A LDO regulator (e.g., LP38690) for the core rail to maintain regulation under load transients.
Estimated: Typical power dissipation for a 50% utilized APEX 20KC running at 100 MHz is approximately 1.5-2.5 W. Designers often underestimate I/O bank power - each LVDS output pair adds 10-15 mA. For configuration, ensure MSEL0/1/2 are tied to correct logic levels for the chosen mode (Passive Serial vs JTAG vs Fast Passive Parallel). Mistaking MSEL settings is the most common board bring-up failure. Also verify the JTAG chain order if multiple devices are cascaded - the EP20K600CF672I9 must appear in the chain file with its correct IR length of 10.
Route high-speed I/O (LVDS, clock) on inner layers with ground reference to minimize EMI. Maintain 100 Ω differential impedance for LVDS pairs and 50 Ω single-ended for LVCMOS/PCI signals. Keep clock inputs (CLK0-3) short and shielded by ground pours - these feed the PLL inputs and excessive trace length degrades jitter. Place the configuration EEPROM or flash within 2 inches of the FPGA in Passive Serial mode to minimize programming time and signal integrity issues during in-system reconfiguration.
Compliance Information
Compliance data (RoHS, REACH, lead-free, halogen-free) not found in the verified web data; marked as 'unknown'. The APEX 20KC family was launched in the early 2000s and pre-dates many current compliance documentation requirements. AEC-Q100 is not applicable as this is an industrial-grade FPGA, not an automotive-qualified part.
