EP20K600EFC672-2N - 600K Gates APEX 20KE FPGA 672-FBGA | Intel
MPN: EP20K600EFC672-2N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $245 | $245.00 |
| 10 | $220 | $2,200.00 |
| 100 | $195 | $19,500.00 |
| 500 | $175 | $87,500.00 |
| 1,000 | $158 | $158,000.00 |
EP20K600EFC672-2N Overview
A Field Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), embedded memory blocks, and programmable interconnect that the user defines after manufacture using a hardware description language (HDL) and a vendor-specific tool flow. The APEX 20KE family sits in the wider taxonomy of programmable logic devices (PLDs), which also includes Simple PLDs (SPLDs) and Complex PLDs (CPLDs); FPGAs are distinguished by their very high logic density, distributed RAM, and on-chip features such as PLLs and LVDS I/O.
Key features of the EP20K600EFC672-2N include 311,296 bits of embedded system memory distributed across embedded array blocks (EABs), four phase-locked loops (PLLs) for clock management, multi-standard I/O supporting LVTTL, LVCMOS, PCI, and LVDS, and an internal core voltage of 1.8 V with multi-voltage I/O banks. The device supports system speeds up to 200 MHz and is rated for commercial operating temperatures of 0 °C to 85 °C. The 672-ball FC-FBGA package offers high-density interconnect in a surface-mount footprint.
Architecturally, APEX 20KE combines look-up-table-based logic elements (LEs) with EAB memory blocks, allowing designers to implement large datapaths, on-chip dual-port RAM, ROM, and content-addressable memories without external components. The four PLLs provide on-chip frequency synthesis, multiplication, division, and skew control, eliminating external clock-generation chips in most designs.
Typical applications include high-speed digital signal processing (DSP), telecommunications infrastructure such as SONET/SDH framer and line-card designs, PCI and high-bandwidth bus interfaces, custom coprocessor and accelerator logic, and protocol bridging. The 508 user I/Os make the part suitable for designs that must aggregate many external buses.
Designers should plan board layout to accommodate the 1.27 mm pitch BGA, provide matched-length clocks for the PLLs, and use Intel/Altera Quartus II (or MAX+PLUS II for legacy flows) for place-and-route and bitstream generation. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EP20K600EFC672-2N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600EFC672-2N (same form factor and footprint) — differing in Operating Temperature, RoHS Status, Package, Speed Grade, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600EFC672-1XN
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$285 / Unit
View Datasheet →EP20K600EFC672-2X
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$115 / Unit
View Datasheet →EP20K600EFC672-3N
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K600EFC672-1X
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$980 / Unit
View Datasheet →EP20K600EFC672-2
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K600EFC672-2N Maximum Ratings & Electrical Characteristics
| Family | APEX 20KE |
| Device Type | SPLD / FPGA |
| System Gates | 600,000 |
| Logic Elements / Cells | 24,320 |
| Embedded Memory (bits) | 311,296 |
| Macros | 2432 |
| Maximum User I/O | 508 |
| Package | 672-pin FC-FBGA (27 × 27 mm) |
| Ball Pitch | 1.27 mm |
| Propagation Delay | 1.48 ns |
| Internal Frequency (max) | 200 MHz |
| Core Voltage | 1.8 V |
| I/O Voltage | Multi-voltage (LVTTL/LVCMOS/PCI/LVDS) |
| Process Technology | 0.15 µm all-layer copper CMOS |
| PLLs | 4 |
| Operating Temperature | 0 °C to 85 °C (commercial) |
| Mounting Type | Surface Mount |
| Lead-Free | Yes (per Altera Lead Free equivalent listing) |
| RoHS Status | Compliant |
EP20K600EFC672-2N 672-pin fc-fbga (27 × 27 mm) Pin Configuration Guide
Pin configuration for EP20K600EFC672-2N (672-pin fc-fbga (27 × 27 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K600EFC672-2N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K600EFC672-2N is suitable for 6 applications: Telecommunications Line Cards (SONET/SDH Framing), High-Speed Digital Signal Processing (DSP) Datapaths, Custom Coprocessor / Accelerator Logic, PCI / CompactPCI / PMC Card Designs, Industrial Control and Custom Bus Bridging, Legacy ASIC/ASSP Replacement and Long-Life Migrations.
Telecommunications Line Cards (SONET/SDH Framing)
The EP20K600EFC672-2N fits SONET/SDH line-card and framer designs because its 600K system gates and 311 Kbits of embedded EAB memory implement STS-1/STM-1 framers, pointer processors, and overhead extractors in a single device. The four on-chip PLLs derive multiple reference clocks (e.g. 19.44 MHz, 77.76 MHz, 155.52 MHz) from a single board oscillator, eliminating external clock-generator chips and reducing BOM cost. With 508 user I/Os the FPGA can aggregate 16+ E1/T1 links plus a UTOPIA/POS-PHY interface to a network processor. Designers typically target ~120 MHz system clock with margin below the 200 MHz fMAX, yielding comfortable timing closure in Quartus II for STS-3/STM-1 designs.
Recommended
High-Speed Digital Signal Processing (DSP) Datapaths
The EP20K600EFC672-2N's 24,320 logic elements and 311 Kbits of distributed EAB RAM make it well-suited to FIR filters, FFT/iFFT engines, and Reed-Solomon codecs at sample rates up to 80-120 MHz. Embedded array blocks (EABs) implement multiplier-accumulator (MAC) arrays by mapping coefficients into RAM, freeing logic for datapath control. The 200 MHz internal fMAX and dedicated PLL-based clock multiplication let one device service both the system clock and a higher DSP sample clock from a single low-jitter reference. Designers report fitting 256-tap FIR filters or 1024-point complex FFTs within ~70% of the device, leaving headroom for control logic and LVDS I/O glue.
Recommended
Custom Coprocessor / Accelerator Logic
The EP20K600EFC672-2N is commonly used as a PCI-bus-attached coprocessor offloading compute-intensive tasks (encryption, image processing, packet classification) from a host CPU. The 508 user I/Os support 64-bit PCI at 66 MHz, multi-bank SDRAM interfaces, and high-speed LVDS links to companion DSPs or ASICs. Four PLLs allow independent clock domains for PCI, SDRAM, and the accelerator core. Designers typically place the FPGA between a PowerPC or x86 host and 2-4 banks of external ZBT/SSRAM, achieving 1-2 GB/s sustained throughput for bulk data movement. Quartus II place-and-route with LogicLock regions enables IP reuse across product variants.
Recommended
PCI / CompactPCI / PMC Card Designs
The APEX 20KE's PCI-compliant I/O and 508 user I/O count make the EP20K600EFC672-2N a natural fit for PCI, CompactPCI, and PMC mezzanine cards in industrial and telecom platforms. The device implements 32-bit/33 MHz or 64-bit/66 MHz PCI target/master interfaces, scatter-gather DMA engines, and I/O expansion logic for rear-panel connectivity. Embedded EAB RAM holds descriptor rings and on-chip packet buffers, reducing external memory accesses. The 672-FBGA package allows high-density board layouts with controlled-impedance routes to the PCI connector and companion local bus devices.
Recommended
Industrial Control and Custom Bus Bridging
Beyond telecom and DSP, the EP20K600EFC672-2N is widely used in industrial control backplanes where it bridges legacy buses (VME, ISA, VXI) to modern serial fabrics and implements custom real-time control logic. The 508 user I/Os aggregate many parallel sensor/actuator lines, while the four PLLs synchronize multiple isolated clock domains (sensor sampling, motor control, host interface). Industrial users value the APEX 20KE's deterministic logic-element architecture and Quartus II's deterministic timing analysis, which simplify safety certification for machinery. Commercial 0-85 °C operation covers most factory-floor enclosures.
Recommended
Legacy ASIC/ASSP Replacement and Long-Life Migrations
The EP20K600EFC672-2N is frequently used as a form-fit-function replacement for obsolete ASICs and ASSPs in long-life programs (military, aerospace, medical equipment) where requalification cost dominates. Drop-in compatibility with the -2 and -2X speed grades means existing PCBs, schematics, and Quartus II bitstreams can be re-used without layout rework. Verified Web Data confirms the -2N is the lead-free equivalent of the -2X (Altera Lead-Free Cross Reference, community reference 89222), so programs migrating from Pb to Pb-free manufacturing can substitute directly. For new designs, however, Intel recommends migrating to Cyclone IV/V or MAX 10 to avoid future obsolescence.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600EFC672-2N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600EFC672-1XN | EP20K600EFC672-2X | EP20K600EFC672-3N | EP20K600EFC672-1X | EP20K600EFC672-2 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-FBGA (27×27 mm) | 672-FBGA (27×27 mm) - same | 672-FBGA (27×27 mm) - same | 672-FBGA (27×27 mm) - same | 672-FBGA (27×27 mm) - same | 672-FBGA (27×27 mm) - same |
| System Gates | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 |
| Logic Elements | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 |
| Embedded Memory (bits) | 311,296 | 311,296 | 311,296 | 311,296 | 311,296 | 311,296 |
| Maximum User I/O | 508 | 508 | 508 | 508 | 508 | 508 |
| Speed Grade | -2 | -1 (slower) | -2 (same) | -3 (faster) | -1 (slower) | -2 (same) |
| Lead-Free | Yes | Yes | No (Pb-bump) | Yes | No (Pb-bump) | No (Pb-bump) |
| Operating Temperature | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Lead-free drop-in for legacy -2X designs (vs EP20K600EFC672-2X)
- Higher fMAX than -1 speed grade (vs EP20K600EFC672-1XN)
- Lower cost than -3 speed grade (vs EP20K600EFC672-3N)
Design Notes
The 672-ball FC-FBGA uses 1.27 mm ball pitch on a 27 × 27 mm body. Use a minimum 6-layer PCB stackup with dedicated ground and power planes directly under the BGA to provide low-impedance return paths and thermal spreading. Escape routing should use 0.20 mm (8 mil) trace-and-space on the top layer with microvia-in-pad (0.30 mm diameter pad, 0.10 mm via) for inner-row balls; non-signal balls may be replaced with thermal vias stitched to internal ground planes to drop theta-JA by 15-25%.
All four PLLs require clean, low-jitter reference clocks; place clock-input pins adjacent to a PLL and route with 50 Ω controlled impedance and matched length to its companion output pair (typically within 0.5 mm). Use a pi-filter (ferrite bead + bypass caps) on each PLL VCC pin to isolate PLL analog supply from digital switching noise. Skew between PLL output clocks feeding DDR/SDRAM interfaces must be held below 50 ps; use length-matching with serpentine tuning rather than relying on package skew alone.
Estimated: at 200 MHz, full I/O switching, and 1.8 V core, the EP20K600EFC672-2N typically dissipates 2.5 to 4.0 W. With a 27 × 27 mm FC-FBGA and standard JEDEC EIA/JESD51 test board (theta-JA ≈ 18 °C/W), junction temperature rise is roughly 45 to 72 °C above ambient. For forced-air-cooled chassis above 60 °C inlet, derate the design or add a heat spreader bonded to the package top with thermal-interface material to keep Tj below 125 °C.
Do not confuse the EP20K600EFC672-2N (lead-free) with the EP20K600EFC672-2X (Pb-bump) - both share the same die and footprint but require different solder pastes and reflow profiles per IPC J-STD-020. Also verify Quartus II version: APEX 20KE is supported only up to Quartus II v13.0sp1; MAX+PLUS II is end-of-life. For boundary-scan and JTAG ISP, dedicate a 4-wire JTAG header per IEEE 1149.1 and tie TRST to ground through a 1 kΩ resistor - leaving TRST floating is a common cause of configuration failure on APEX 20KE boards.
Compliance Information
Lead-free ('N' suffix) confirmed by Altera Lead-Free Cross Reference (community reference 89222). RoHS compliance inferred from lead-free terminal finish; no explicit RoHS statement in Verified Web Data. AEC-Q100 not applicable for commercial-grade FPGAs.
