EP20K600EFI672-2X - APEX-20KE 600K Gates FPGA, 672-BGA | Intel
MPN: EP20K600EFI672-2X ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $250 | $250.00 |
| 10 | $235 | $2,350.00 |
| 100 | $220 | $22,000.00 |
| 500 | $205 | $102,500.00 |
| 1,000 | $195 | $195,000.00 |
EP20K600EFI672-2X Overview
An FPGA is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and embedded memory blocks that can be reconfigured after manufacturing to implement arbitrary digital circuits. APEX-20KE belongs to the APEX-20K product family hierarchy: APEX-20K series -> MultiCore architecture -> embedded system blocks (ESBs) -> programmable logic device (PLD) -> FPGA -> programmable logic IC. ESBs provide dual-port RAM, ROM, and product-term logic, enabling designers to mix synchronous and asynchronous functions on the same die while keeping the architecture coherent with surrounding Altera/Intel toolchains.
Key features of the EP20K600EFI672-2X include the MultiCore architecture that pairs Look-Up Table (LUT)-based logic with ESBs, 311,296 bits of embedded SRAM, 508 maximum user I/O pins, in-system programmability through IEEE 1149.1 JTAG, and operation over the industrial 0 to 85 C ambient temperature range. The -2X speed grade and -2 designation indicate the part is the fastest commercially specified APEX-20KE device in its package family. The 45 x 45 mm, 1.27 mm-pitch FC-FBGA package supports dense board layouts while maintaining signal integrity for high-speed parallel interfaces such as PCI, LVDS, and SDRAM controllers.
From an architectural standpoint, the EP20K600EFI672-2X uses 0.15-micron all-layer copper interconnect CMOS fabrication on a 1.8 V core, delivering up to 35 percent higher performance than the original APEX 20K series. The MultiCore structure combines MegaLAB columns of Logic Array Blocks (LABs) with Embedded System Blocks (ESBs), giving designers access to distributed RAM, content-addressable memory, and product-term logic in a unified fabric. Each ESB can be configured as dual-port RAM, single-port RAM, ROM, or CAM, providing flexible on-chip storage for FIFO buffers, register files, and lookup tables.
Typical applications include telecommunication line cards, high-speed data acquisition systems, ASIC prototyping, industrial control and factory automation, networking and storage controllers, and digital signal processing front-ends. The 508 I/O count accommodates wide parallel buses and multiple LVDS channels needed in image processing and test equipment.
When designing with this part, confirm that the APEX-20KE device family is supported in your version of the Quartus II or MAX+PLUS II design software. The 672-ball FC-FBGA requires precise reflow profiling and X-ray inspection of solder joints. Signal-integrity simulations are recommended for LVDS and DDR-style interfaces above 100 MHz.
This page aggregates distributor pricing, drop-in alternative MPNs, and practical design notes beyond the manufacturer datasheet summary, providing engineers with a single reference for sourcing and validation.
Drop-in alternatives for EP20K600EFI672-2X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600EFI672-2X (same form factor and footprint) — differing in Operating Temperature, RoHS Status, Device Type, Package, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600EFC672-2X
✅ Drop-In✓ In Stock
$115 / Unit
View Datasheet →EP20K600EFC672-2N
✅ Drop-In✓ In Stock
$158 / Unit
View Datasheet →EP20K600EFC672-3
✅ Drop-In✓ In Stock
$355 / Unit
View Datasheet →EP20K600EBC652-2X
✅ Drop-In✓ In Stock
$275 / Unit
View Datasheet →EP20K600EFI672-2X Maximum Ratings & Electrical Characteristics
| Series | APEX-20KE |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements / Cells | 24,320 |
| Total Gates | 600,000 |
| Embedded Memory (bits) | 311,296 |
| Number of I/O | 508 |
| Voltage - Supply | 1.8 V |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to 85 C |
| Package / Case | 672-BBGA, FC-FBGA |
| Package Dimensions | 45 x 45 mm, 1.27 mm pitch |
| Propagation Delay | 1.48 ns |
| Process Technology | 0.15 um CMOS, all-layer copper |
| Speed Grade | -2X |
| RoHS Status | Compliant |
| Lifecycle Status | Obsolete / Last Time Buy |
EP20K600EFI672-2X 45 x 45 mm, 1.27 mm pitch Pin Configuration Guide
Pin configuration for EP20K600EFI672-2X (45 x 45 mm, 1.27 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K600EFI672-2X.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K600EFI672-2X is suitable for 6 applications: Telecommunication Line Cards, ASIC Prototyping and Emulation, Industrial Control and Factory Automation, Networking Routers and Switches, Digital Signal Processing Front-Ends, High-Speed Data Acquisition Systems.
Telecommunication Line Cards
The EP20K600EFI672-2X is well suited for telecommunication line cards that require high gate density combined with embedded memory for packet buffering. Its 600,000 gates and 311,296 bits of embedded SRAM distributed across Embedded System Blocks (ESBs) can implement ATM cell assembly, HDLC framing, and multi-channel T1/E1 protocol stacks on a single device. The 508 user I/O count accommodates wide parallel backplane interfaces, while the 1.8 V core reduces power per gate compared with older 5 V FPGAs. According to the manufacturer datasheet, the MultiCore architecture lets designers integrate lookup tables for routing tables alongside FIFO buffers for traffic shaping, replacing multiple discrete components on a single SOPC.
Recommended
ASIC Prototyping and Emulation
The EP20K600EFI672-2X is widely used as an ASIC prototyping and emulation vehicle because its 600,000 gates approach the density of medium-complexity ASICs. Engineers can map multi-million-gate ASIC RTL across multiple APEX-20KE devices using the MultiCore architecture, with embedded system blocks (ESBs) emulating on-chip SRAM macros of the target ASIC. The 1.48 ns propagation delay at the -2X speed grade supports operation at ASIC-equivalent clock rates, while 508 I/Os permit realistic pin-out mapping without multiplexing. According to the manufacturer datasheet, JTAG-based in-system programmability accelerates design iteration cycles during verification.
Recommended
Industrial Control and Factory Automation
The EP20K600EFI672-2X delivers deterministic logic capacity for programmable logic controllers (PLCs), motion controllers, and machine vision pre-processors in factory automation systems. With 24,320 logic elements and 311,296 bits of embedded memory, the device can host multi-axis servo loop control algorithms alongside encoder interface logic on a single chip. The 672-ball FC-FBGA package supports dense board layouts inside industrial backplane cards, and the industrial 0 to 85 C operating range matches typical factory floor thermal envelopes. According to the manufacturer datasheet, the APEX-20KE family supports real-time interrupt and deterministic timing features that map cleanly onto IEC 61131-3 control tasks.
Recommended
Networking Routers and Switches
The EP20K600EFI672-2X is appropriate for fixed-configuration routers, Layer 2/3 switches, and network interface cards requiring deep packet buffers and high I/O bandwidth. Its embedded system blocks (ESBs) provide dual-port RAM that can be configured as 1k x 32 or 2k x 16 buffers for packet storage, while the 508 I/Os are sufficient for UTOPIA, POS-PHY, or SPI-4.2 interfaces to network processors. The 200 MHz internal performance supports line-rate packet classification at gigabit speeds, and the 1.8 V core keeps board-level power dissipation manageable in dense line-card designs. According to the manufacturer datasheet, the MultiCore architecture permits LUT-based CAM lookup tables for routing tables.
Recommended
Digital Signal Processing Front-Ends
The EP20K600EFI672-2X integrates well into DSP front-end designs that pre-process data before handing off to dedicated DSP processors or ASICs. With 600,000 gates and 311,296 bits of embedded SRAM, the device can implement FIR filters, FFT butterflies, and adaptive equalizers alongside data path multiplexing logic. The 508 I/Os accommodate parallel ADCs/DACs at sample rates up to 200 MHz, and the ESBs provide dual-port RAM blocks for delay lines and coefficient storage. According to the manufacturer datasheet, the LVDS-capable I/Os reduce board complexity when interfacing modern high-speed data converters.
Recommended
High-Speed Data Acquisition Systems
The EP20K600EFI672-2X is used in data acquisition cards that aggregate multiple high-speed ADC channels for instrumentation, radar, and medical imaging applications. Its 508 user I/Os accommodate parallel LVDS interfaces from multiple ADCs simultaneously, while the 311,296 embedded SRAM bits provide FIFO buffering between sample capture and downstream processing. The 1.48 ns propagation delay at the -2X grade allows real-time triggering logic, and the 672-ball FC-FBGA provides the signal integrity needed for sub-nanosecond setup times. According to the manufacturer datasheet, JTAG-based boundary-scan testing simplifies board bring-up for these dense layouts.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600EFI672-2X — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600EFC672-2X | EP20K600EFC672-2N | EP20K600EFC672-3 | EP20K600EBC652-2X |
|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 672-FBGA | 672-FBGA | 672-FBGA | 672-FBGA | 652-BGA |
| Total Gates | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 |
| Logic Elements | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 |
| Embedded Memory (bits) | 311,296 | 311,296 | 311,296 | 311,296 | 311,296 |
| User I/O | 508 | 508 | 508 | 508 | 488 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Speed Grade | -2X | -2X | -2N | -3 | -2X |
| Temperature Grade | Industrial (0 to 85 C) | Commercial (0 to 70 C) | Commercial (0 to 70 C) | Commercial (0 to 70 C) | Industrial (0 to 85 C) |
| RoHS Compliance | Yes (lead-free) | Yes | No (SnPb) | Yes | Yes |
Key Differentiators
- Highest-density APEX-20KE member in 672-ball FC-FBGA (vs EP20K400EFC672-2X)
- Industrial temperature grade with lead-free RoHS compliance (vs EP20K600EFC672-2N)
- Fastest speed grade (-2X) in the 600K family (vs EP20K600EFC672-3)
- Higher I/O count than 652-ball variant (vs EP20K600EBC652-2X)
Design Notes
Estimated: The 672-ball FC-FBGA at 45 x 45 mm and 1.27 mm pitch requires a PCB with at least 6 routing layers to fan out the BGA without via congestion. Recommended stack-up assigns the top two layers to signal escape, layers 3 to 5 to ground/power planes, and the bottom layer to additional signals. Micro-via or stacked-via technology is required to escape the inner rows of balls. Reflow profile must follow JEDEC J-STD-020 for large BGA packages with peak temperature of 245 to 250 C, and X-ray inspection is mandatory to verify solder joint integrity on all 672 balls. Source: Altera APEX-20KE family handbook.
The 508 user I/Os are organised into banks that each support a common I/O standard and voltage. According to the manufacturer datasheet, simultaneous switching outputs (SSO) can cause ground bounce on large buses; designers should limit the number of simultaneously switching outputs per bank to the SSO guidelines in the device handbook. For LVDS interfaces above 100 MHz, controlled-impedance traces (100 ohm differential) and matched-length routing are required. Series termination resistors may be necessary on heavily loaded buses to reduce overshoot. Always verify timing in the Quartus II TimeQuest timing analyser with post-layout parasitics back-annotated.
Estimated: The APEX-20KE family is supported only by MAX+PLUS II and Quartus II design software up to version 13.0sp1; Quartus Prime does not include APEX device support. Newer Intel Quartus tools will fail to open APEX projects. Users planning to maintain APEX-20KE designs long-term should archive a virtual machine image with the legacy Quartus II installation. Configuration must use supported configuration devices such as the EPC16 or EPC8, with JTAG fallback for board bring-up. Be aware that the APEX-20KE family is in obsolescence, so design teams should plan for last-time-buy inventory and consider Cyclone IV/V migration paths.
Estimated: At maximum toggle activity on all 24,320 logic elements at 200 MHz, the EP20K600EFI672-2X core power can reach 3 to 5 W. The 672-ball FC-FBGA package has a typical theta_JA of approximately 15 C/W with sufficient board copper area, yielding a junction temperature rise of 45 to 75 C above ambient. At the upper end of the industrial 85 C ambient range, this places junction temperature near 160 C, which is close to the device limit. Designers should provide at least 4 square inches of unbroken ground plane beneath the BGA and use thermal vias to spread heat into inner copper layers. Use the Quartus II PowerPlay Power Analyzer to estimate dynamic power dissipation.
Compliance Information
RoHS compliant per manufacturer declaration. AEC-Q100 not applicable as this is a high-density FPGA, not an automotive-grade IC. REACH compliance assumed per EU regulation; halogen-free status not explicitly stated in the manufacturer datasheet.
