EP2A70B652C9 - APEX II 70K LE FPGA, BGA-652 | Intel
MPN: EP2A70B652C9 ✗ End of Life| Qty | Unit Price | Extended |
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| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
EP2A70B652C9 Overview
An FPGA (Field Programmable Gate Array) is a type of integrated circuit containing an array of programmable logic blocks, configurable interconnects, and dedicated I/O cells that can be reconfigured after manufacturing to implement arbitrary digital logic. FPGAs sit in the programmable logic device (PLD) hierarchy, below CPLDs in density and above PALs/GALs. They are widely used for ASIC prototyping, low-volume custom logic, DSP acceleration, and parallel data-path applications where time-to-market and hardware flexibility outweigh the per-unit cost advantage of cell-based ASICs. APEX II was Intel's (formerly Altera) second-generation multi-gigabit, multi-volt family before being superseded by Stratix and subsequent families.
Key features of the EP2A70B652C9 include dedicated on-chip memory blocks, embedded LVDS-capable I/O with multi-voltage support (1.5V, 1.8V, 2.5V, 3.3V), integrated PLLs for clock management, and up to 12 high-speed transceiver channels on speed-grade variants. The BGA-652 package supports up to 8 banks of user I/O, with routing density sufficient for memory-rich designs. Speed grade C9 places it in a moderate performance class within the APEX II lineup.
Architecturally, APEX II uses a MultiCore architecture combining fine-grain logic elements (LEs) with MegaLAB blocks that include embedded array blocks (EABs) for efficient memory and multiplier implementation. The 7-level routing hierarchy provides a balance between performance predictability and routing flexibility. Multi-gigabit transceivers and True-LVDS support allow direct interfacing with high-speed backplanes and memory interfaces such as QDR and DDR SRAM.
Typical applications include high-bandwidth telecommunications line cards, ASIC prototyping for SoC designs, custom DSP accelerators in medical imaging and radar signal processing, and high-speed serial protocol bridging. The combination of high logic density and on-chip memory makes it particularly suited for pipeline-parallel algorithms and protocol conversion functions.
When designing with this part, consider the device's discontinued status in the Intel/Altera product catalog and use the open-source Quartus II design software for synthesis, place-and-route, and timing closure. Power estimation should use the PowerPlay tool within Quartus II before final board design.
This page synthesizes distributor inventory signals, drop-in compatible alternatives, and practical FPGA design guidance not consolidated in the manufacturer's datasheet, supporting engineers sourcing long-lifecycle or end-of-life APEX II inventory.
Drop-in alternatives for EP2A70B652C9 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2A70B652C9 (same form factor and footprint) — differing in Package, Speed Grade, Family, Mounting Type, I/O Bank Voltage (VCCIO).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2A70B652C8
✅ Drop-In✓ In Stock
$275 / Unit
View Datasheet →EP2A70B652C7
✅ Drop-In✓ In Stock
$10.506 / Unit
View Datasheet →EP2A70B652C9 Maximum Ratings & Electrical Characteristics
| Family | APEX II |
| Logic Cells | 67,200 |
| Process Technology | 0.18 um CMOS |
| Package | BGA-652 |
| Speed Grade | C9 |
| Supply Voltage - Core | 1.8 V |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Embedded Memory | EAB-based RAM blocks |
| Operating Temperature | -40C to +85C (industrial range, to be confirmed) |
| Mounting Type | Surface Mount (BGA) |
| Design Software | Quartus II (legacy, APEX II support) |
EP2A70B652C9 bga-652 Pin Configuration Guide
Pin configuration for EP2A70B652C9 (bga-652 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2A70B652C9.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2A70B652C9 is suitable for 6 applications: ASIC Prototyping, Telecommunications Line Cards, Custom DSP Accelerators, High-Speed Protocol Bridging, Medical Imaging Front-End, Industrial Control and Automation.
ASIC Prototyping
The EP2A70B652C9's 70K LE density and embedded EAB memory blocks make it well suited for ASIC prototyping, where engineers map a target ASIC netlist onto an FPGA for in-system validation before tape-out. The APEX II MultiCore architecture preserves RTL synthesis fidelity through Quartus II, and the BGA-652 package exposes enough I/O for mid-complexity SoC prototypes. The C9 speed grade is sufficient for functional validation, while C8 or faster grades may be required for timing-accurate emulation. Compared with ASIC verification using dedicated emulators, the APEX II approach trades off speed for cost-effectiveness, making it ideal for pre-silicon software development, IP integration verification, and design bring-up in sub-1M gate designs.
Recommended
Telecommunications Line Cards
The EP2A70B652C9's True-LVDS capable I/O and high-density logic fabric support telecommunications line cards that require high-speed serial-to-parallel conversion and custom packet processing. Its multi-voltage I/O banks (1.5V/1.8V/2.5V/3.3V) interface directly to legacy bus interfaces and modern SERDES phys without external level shifting. The device's embedded EAB memory enables on-chip buffering for packet queue management. APEX II was commonly deployed in early-generation SONET/SDH and ATM equipment; replacement designs in modern telecom gear should target Stratix IV or later families with hardened transceivers, but APEX II remains in service in legacy infrastructure requiring long-term support windows of 10+ years.
Recommended
Custom DSP Accelerators
The EP2A70B652C9's high logic density and embedded EAB memory blocks make it suitable for custom DSP accelerator cards in medical imaging, radar signal processing, and software-defined radio. The MultiCore architecture supports parallel FIR/FFT pipelines and matrix multiplication, with on-chip EABs providing coefficient and sample memory without external SRAM access penalties. The BGA-652 package supports up to several hundred user I/O, sufficient for multi-channel ADC/DAC interfacing. The C9 speed grade achieves Fmax in the 150-200 MHz range for typical DSP paths. For new designs requiring >200 MHz DSP throughput, migrate to Stratix III or Cyclone V families with dedicated DSP blocks.
Recommended
High-Speed Protocol Bridging
The EP2A70B652C9 can implement custom protocol bridges between legacy parallel buses (PCI, VME, ISA) and modern serial protocols (SPI, I2C, custom LVDS), making it valuable in industrial retrofit and test equipment designs. Its True-LVDS support and multi-voltage I/O enable direct interfacing with mixed-voltage subsystems without glue logic. The 70K LE fabric supports RTL-based state machines, FIFOs, and protocol stacks in a single device. Bridge designs benefit from the embedded EAB memory for packet buffering. APEX II remains deployed in long-lifecycle industrial controllers where bridge functionality must match 20-year equipment support expectations.
Recommended
Medical Imaging Front-End
The EP2A70B652C9's logic density and embedded memory support medical imaging front-end preprocessing in ultrasound, CT, and MRI subsystems. Pixel-level preprocessing pipelines, beamforming algorithms, and image reconstruction kernels map efficiently onto the APEX II MultiCore architecture. The BGA-652 package's high I/O count accommodates parallel ADC interfaces from ultrasound transducer arrays. Long product lifecycles in medical imaging (15-20 years) make legacy FPGA families like APEX II economically attractive for incremental feature updates to existing equipment platforms. New medical imaging designs should consider Cyclone V or Stratix 10 with hardened DSP blocks and lower power consumption.
Recommended
Industrial Control and Automation
The EP2A70B652C9's industrial temperature range and high logic density suit Programmable Logic Controller (PLC) and motion controller applications where deterministic, parallel processing of sensor inputs is required. The device's MultiCore architecture supports multiple independent control loops running concurrently with hardware-level determinism impossible in software PLCs. Embedded EAB memory provides local storage for control tables and state machines. APEX II was widely deployed in industrial motion controllers, CNC machines, and robotic systems in the 2000s and remains in service due to long equipment lifetimes. Designs requiring IEC 61508 SIL certification should consult the device's safety documentation carefully, as APEX II predates modern functional safety certification programs.
Recommended
Recommended Products Summary
Engineering reference data for EP2A70B652C9 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2A70B652C8 | EP2A70B652C7 |
|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | BGA-652 | BGA-652 - same | BGA-652 - same |
| Family | APEX II | APEX II | APEX II |
| Logic Cells | 67,200 | 67,200 - same | 67,200 - same |
| Speed Grade | C9 | C8 (faster) | C7 (slower) |
| Logic Elements | ~70,000 | ~70,000 - same | ~70,000 - same |
| Core Voltage | 1.8 V | 1.8 V - same | 1.8 V - same |
| Lifecycle Status | Obsolete | Obsolete | Obsolete |
| Design Toolchain | Quartus II (legacy) | Quartus II (legacy) | Quartus II (legacy) |
Key Differentiators
- Mid-range speed grade offering balance of performance and availability (vs EP2A70B652C8)
- Slower speed grade enables cost-effective sourcing for non-timing-critical designs (vs EP2A70B652C7)
- Full BGA-652 I/O complement vs. lower-density APEX II parts (vs EP2A40B652C9)
Design Notes
The EP2A70B652C9 requires Altera/Intel Quartus II design software with explicit APEX II device support. Modern Quartus Prime releases do not include APEX II support; retain a Quartus II installation (version 13.0 or earlier with APEX II support enabled) for synthesis, place-and-route, and bitstream generation. Attempting to import APEX II designs into newer Quartus Prime releases will fail at the device-selection stage, so maintain version compatibility throughout the design flow.
Estimated: At typical APEX II utilization of 60-70% logic and 100 MHz operation, the EP2A70B652C9 dissipates approximately 2-4 W. The BGA-652 package requires careful PCB thermal design - implement at least 4 thermal vias in the BGA center array under the die and use a 4-layer PCB with a dedicated ground/power plane to spread heat. Add a heatsink or thermal pad interface for designs operating at >3 W continuous dissipation. The exact thermal resistance (theta_JB and theta_JA) is documented in the APEX II device family datasheet.
BGA-652 requires reflow soldering with precise temperature profiles (peak 245-260 C, ramp 2-3 C/s, soak 60-90 s) and PCB land patterns per IPC-7351 BGA guidelines. Stencil aperture design should use 0.4 mm solder balls with 0.5 mm paste apertures for proper joint formation. Under-fill is recommended for high-vibration or thermal-cycling applications (industrial, automotive). X-ray inspection after reflow is strongly recommended to verify joint integrity, as BGA-652 solder joints are inaccessible for visual inspection.
Multi-voltage I/O banks must have their VCCIO supplies decoupled with 0.1 uF ceramic capacitors placed within 5 mm of each supply pin, plus a bulk 10 uF tantalum or ceramic capacitor per bank. Differential pairs (LVDS) require 100 ohm differential impedance with matched trace lengths within 150 mil to maintain timing margin. Use the Quartus II pin planner and signal integrity tools to validate impedance and crosstalk before PCB fabrication. Bank-to-bank skew should be verified with the on-chip PLL configurations.
Configuration memory on the EP2A70B652C9 is SRAM-based and volatile; the bitstream must be loaded from a configuration ROM (EPC configuration device) on every power-up. Select an EPC configuration device sized for the EP2A70B652C9 bitstream (typically 4-8 Mbit depending on compression). Designs requiring instant-on behavior or fail-safe operation should consider a separate watchdog CPLD to supervise configuration. Do not assume the FPGA retains its configuration across power cycles.
Compliance Information
APEX II devices predate RoHS enforcement. RoHS/REACH/lead-free status not explicitly confirmed in available distributor data. Request declarations from distributor at time of quote. AEC-Q100 not applicable for commercial/industrial FPGA.
