Intel

EP2AGX65DF25I3N - Arria II GX FPGA, 60K LE, 252 I/O, 572-FCBGA | Intel

MPN: EP2AGX65DF25I3N ⚠ Last Time Buy

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0.9 V Vdss 572-ball FCBGA (flip-chip BGA) Package 2,531 Kbits Memory

From $125.9 USD / Unit

MOQ: 1 |

Price updated: 2026-09-08

Volume Pricing

Qty	Unit Price	Extended
1	$209.84	$209.84
10	$188.86	$1,888.60
100	$167.87	$16,787.00
500	$146.89	$73,445.00
1,000	$125.9	$125,900.00

ℹ️ All prices are in USD

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EP2AGX65DF25I3N Overview

The Intel (formerly Altera) EP2AGX65DF25I3N is a member of the Arria II GX family of field-programmable gate arrays, integrating 60,214 logic elements, 2,531 Kbits of embedded memory, and 252 user I/O in a 572-ball flip-chip BGA package. It is fabricated on a 40 nm process and operates from a 0.9 V core supply with transceiver and I/O auxiliary rails. The part is rated industrial temperature grade (-40C to +100C ambient) and is intended for mid-density, transceiver-rich applications such as video bridging, wireless baseband, and PCIe endpoint designs.

A Field Programmable Gate Array (FPGA) is a semiconductor device whose digital logic, interconnect, and I/O behaviour are defined after manufacturing by a configuration bitstream loaded into on-chip SRAM. Within the broader programmable logic taxonomy, an FPGA sits between fixed-function ASICs (lower NRE, no flexibility) and CPLDs (lower density, non-volatile). Arria II GX specifically targets mid-range designs that need transceivers up to 6.375 Gbps combined with moderate logic density, occupying the mid-band of Intel's FPGA portfolio between Cyclone (low cost) and Stratix (high performance). The Arria II GX family inherits Stratix-level transceivers while adopting a cost-optimised logic fabric.

Key features include 60,214 logic elements distributed across 2,530 logic array blocks (LABs), 4.4 Mbits of M9K memory and 1.4 Mbits of MLAB memory, eight 6.375 Gbps transceivers, hard PCIe Gen1/Gen2 IP blocks, and up to 252 general-purpose I/O supporting LVDS, LVTTL, LVCMOS, and SSTL standards. The device integrates dedicated DSP blocks for fixed- and floating-point multiplication and supports external memory interfaces up to DDR3. Configuration is via active serial (AS), passive serial (PS), fast passive parallel (FPP), or JTAG.

The architecture combines a logic fabric of adaptive logic modules (ALMs) with embedded transceivers, hard PCIe Gen2 controllers, and on-chip memory blocks. Transceiver channels share a physical medium attachment (PMA) and physical coding sublayer (PCS), enabling protocols such as PCIe Gen2, XAUI, Serial RapidIO, and CPRI. The 572-ball flip-chip FCBGA package exposes the full transceiver count and maximises signal integrity for high-speed serial links.

Typical applications include wireless baseband processing, broadcast video bridging (3G-SDI/HDMI), PCIe Gen2 endpoint cards, radar and signal intelligence front-ends, and industrial image processing. The 6.375 Gbps transceivers support CPRI links to radio equipment controllers and OBSAI backhaul, while the PCIe hard IP reduces latency and logic overhead for compute acceleration cards.

When designing with this part, allocate a dedicated 0.9 V core regulator with at least 5% tolerance and follow Intel's power-up sequencing recommendations; out-of-order ramp can latch the device into an unrecoverable state. Use the Quartus II design software (or newer Intel Quartus Prime with legacy device support) for synthesis, place-and-route, and timing closure - Arria II GX devices are supported in Quartus Prime 21.1 and earlier. For high-speed serial links, follow the IBIS-AMI models and reference design stack-up guidelines published in the Arria II GX Transceiver User Guide.

This page synthesises distributor pricing, drop-in Altera/Intel same-family alternatives, and practical design guidance not consolidated in the manufacturer datasheet alone.

Drop-in alternatives for EP2AGX65DF25I3N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP2AGX65DF25I3N (same form factor and footprint) — differing in Speed Grade, Package, Process Technology, Operating Temperature, RoHS Status.

EP2AGX65DF25C4G

Intel

Speed Grade: C4

Package: 572-ball FCBGA

Process Technology: 40 nm