EP2S60F672I3N - Stratix II FPGA 60K LE 672-FBGA -40°C to 100°C | Altera
MPN: EP2S60F672I3N ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $168.5 | $1,685.00 |
| 100 | $152 | $15,200.00 |
| 500 | $138.75 | $69,375.00 |
| 1,000 | $125.4 | $125,400.00 |
EP2S60F672I3N Overview
A Field-Programmable Gate Array (FPGA) is a reconfigurable semiconductor device whose logic fabric, routing, and I/O are defined by a user-supplied configuration bitstream. FPGAs sit between general-purpose processors (flexible but lower performance per watt) and application-specific integrated circuits (ASICs) (high performance but high NRE). Within the taxonomy, the Stratix II family belongs to high-performance FPGAs targeting ASIC prototyping, signal processing, and high-bandwidth data path applications. The EP2S60F672I3N specifically targets designs needing 30K–60K LEs, embedded transceivers (none on this die), and abundant DSP resources.
Key features include 12 embedded PLLs for clock synthesis, up to 718 user I/O pins depending on the package, support for external memory interfaces (DDR, DDR2, QDR, RLDRAM), and 1.2 V core with 1.5 V/1.8 V/2.5 V/3.3 V multi-voltage I/O banks with auto-calibrated OCT (on-chip termination). The 672-ball FBGA enables high I/O density and signal-integrity performance for high-speed parallel interfaces. Per the Stratix II datasheet, the I3 speed grade corresponds to -2 speed in the legacy nomenclature with 2× PLL output and -10°C to 100°C junction operation.
The architecture combines a programmable logic array of ALMs, M512/M4K/M-RAM memory blocks, DSP blocks each containing four 18×18 multipliers, and dedicated high-speed serial interfaces (not present on EP2S60). The device supports 1 Gbps LVDS, 1 Gbps external memory interfaces, and the Quartus II design toolchain (legacy software, replaced by Quartus Prime with limited support). Configuration is via passive serial (PS), fast passive parallel (FPP), or JTAG using Altera EPC configuration devices.
Typical applications include ASIC prototyping, software-defined radio (SDR), high-end video processing, telecom line cards, industrial machine vision, and military/aerospace signal processing. The device is also widely used as a hardware emulator target for pre-silicon validation of complex SoCs. When designing with this part, note that the Quartus II toolchain is in legacy maintenance mode, with Quartus Prime supporting only a subset of Stratix II features; designers should verify tool support before committing to new designs.
Drop-in alternatives for EP2S60F672I3N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S60F672I3N (same form factor and footprint) — differing in Speed Grade, Package, RoHS Status, PLLs, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S60F672C5N
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View Datasheet →EP2S60F672I5N
✅ Drop-In📋 Reference alternative (not in catalog)
EP2S60F672C3N
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$1175 / Unit
View Datasheet →EP2S60F672C4N
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View Datasheet →EP2S60F672I4N
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View Datasheet →EP2S60F672C3NGA
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View Datasheet →EP2S60F672I3N Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements (LE) | 60,440 |
| Adaptive Logic Modules (ALM) | 24,176 |
| ALUTs | 48,352 |
| Embedded Memory (bits) | 2,544,192 |
| DSP Blocks | 36 |
| 18×18 Multipliers | 144 |
| PLLs | 12 |
| Maximum User I/O | 718 (package dependent) |
| Process Technology | 90 nm |
| Core Voltage | 1.2 V |
| Internal Clock Frequency (max) | 816.99 MHz |
| Package | 672-ball FC-FBGA |
| Speed Grade | I3 |
| Operating Temperature (Industrial) | -40°C to +100°C |
EP2S60F672I3N 672-ball fc-fbga Pin Configuration Guide
Pin configuration for EP2S60F672I3N (672-ball fc-fbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S60F672I3N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S60F672I3N is suitable for 6 applications: ASIC Prototyping and Hardware Emulation, Software-Defined Radio (SDR) Baseband Processing, Industrial Machine Vision and Image Processing, Telecom Line Card and Packet Processing, Military and Aerospace Signal Processing, Medical Imaging and Diagnostic Equipment.
ASIC Prototyping and Hardware Emulation
The EP2S60F672I3N's 60,440 logic elements and 2.5 Mbit embedded memory make it a workhorse for ASIC prototyping platforms. Per the Stratix II datasheet, each LE maps to approximately 30–35 ASIC gates, so a single device can emulate ~2 million ASIC gates. Designers commonly build 2-FPGA or 4-FPGA partitions for full-chip SoC validation, using LVDS channels at 1 Gbps for inter-FPGA pin multiplexing. The industrial temperature range allows use in lab and field environments. Compared to ASIC tape-out at $1M+ NRE, FPGA prototyping at $185/unit cuts development cost by orders of magnitude. The Quartus II software supports gate-level netlist import from Synopsys DC, enabling true ASIC-equivalent verification. The I3 speed grade is sufficient for sub-100 MHz ASIC clock domains; faster emulated designs require I4/I5 grades.
Recommended
Software-Defined Radio (SDR) Baseband Processing
The EP2S60F672I3N is a workhorse for software-defined radio baseband designs. Its 36 DSP blocks deliver 144 18×18 multipliers for FIR filtering, FFT engines, and channelization, while 2.5 Mbit embedded memory buffers ADC sample streams. The device's 1 Gbps LVDS receivers pair with external high-speed ADCs to digitize IF signals from 70 MHz to 500 MHz. The industrial temperature range enables deployment in outdoor telecom cabinets. Compared to GP-DSPs like TI TMS320C6678, the FPGA offers flexibility to support evolving waveform standards. The lack of integrated transceivers means designers must use external DAC/ADC chips; for integrated transceivers the EP2SGX30 or EP2SGX60 Stratix II GX variants are recommended. The I3 speed grade sustains 250 MHz DSP clock for most baseband processing tasks.
Recommended
Industrial Machine Vision and Image Processing
The EP2S60F672I3N's high logic density and abundant DSP blocks suit real-time image processing applications. Industrial machine vision systems use the FPGA to implement Bayer demosaic, color correction matrix, edge detection (Sobel/Canny), and object detection at line rates exceeding 100 MHz. The 12 embedded PLLs generate pixel clocks, line-scan timing, and GigE Vision reference clocks from a single reference oscillator. The 672-ball FC-FBGA package provides 334 user I/Os to interface with multiple Camera Link or CoaXPress sensors. Compared to GPU-based vision systems, the FPGA offers deterministic latency and lower power (~3–5W typical) — critical for embedded industrial PCs. The industrial temperature rating allows deployment in factory floor enclosures with ambient temperatures up to 70°C without active cooling. The I3 speed grade supports 1080p60 processing.
Recommended
Telecom Line Card and Packet Processing
The EP2S60F672I3N is widely deployed in telecom line cards for packet processing, traffic management, and protocol bridging. Its 2.5 Mbit embedded memory provides large packet buffer storage without external SRAM, while the 36 DSP blocks accelerate QoS classification, encryption (AES, 3DES), and traffic shaping. The 12 PLLs generate multiple clock domains for SONET/SDH, Ethernet, and TDM interfaces. The 672-ball FC-FBGA package supports up to 334 user I/Os, enabling multiple SGMII/SerDes interfaces to TI/Lattice PHY chips. Compared to NPUs (network processors), the FPGA offers lower latency and field upgradability for evolving standards. The industrial temperature range supports central office and outside-plant deployment. The I3 speed grade sustains 200 MHz on the internal bus, sufficient for OC-48/STM-16 line rates.
Recommended
Military and Aerospace Signal Processing
The EP2S60F672I3N is found in many military and aerospace signal processing subsystems, including electronic warfare, radar processing, and secure communications. The 60K LEs implement complex FFT engines, polyphase channelizers, and adaptive filters operating at hundreds of MSPS. The industrial temperature range supports MIL-STD-810 environmental conditions. Many programs source the device under the Defense Logistics Agency (DLA) Standard Microcircuit Drawing (SMD) 5962-03220 series. For higher-grade MIL-PRF-38535 Class V screened parts, the EP2S60F672I3N-NPB variant (tin-lead balls, extended temperature) is available from authorized distributors. The device's long-term availability (last-time-buy) is a critical risk factor; military programs typically execute lifetime buys of 5–10× annual usage. Compared to rad-hard FPGAs (Xilinx Virtex-4QV, Microsemi RTG4), the EP2S60 offers higher density at lower cost but no radiation hardness — it is used in shielded or short-mission applications.
Recommended
Medical Imaging and Diagnostic Equipment
The EP2S60F672I3N serves medical imaging systems including ultrasound, CT scanners, and MRI receivers. The 36 DSP blocks accelerate beamforming in ultrasound, where hundreds of channels require real-time delay-and-sum operations. The 2.5 Mbit embedded memory buffers raw RF samples before image reconstruction. The 1 Gbps LVDS interfaces connect to high-speed ADCs (12–16 bit, 40–80 MSPS) commonly used in medical imaging front-ends. The device's deterministic latency is critical for diagnostic-grade image quality. Compared to ASIC solutions from GE Healthcare or Philips, FPGA-based designs offer faster time-to-market for new probe technologies. The industrial temperature range suits controlled clinical environments. Designers must validate that the legacy Quartus II toolchain's certification status (IEC 62304, ISO 13485) meets their quality system requirements — many medical OEMs now migrate to newer Altera/Intel devices with active tool support.
Recommended
Recommended Products Summary
Engineering reference data for EP2S60F672I3N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S60F672C5N | EP2S60F672I5N | EP2S60F672C3N | EP2S60F672C4N | EP2S60F672I4N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 672-ball FC-FBGA | 672-ball FC-FBGA | 672-ball FC-FBGA | 672-ball FC-FBGA | 672-ball FC-FBGA | 672-ball FC-FBGA |
| Logic Elements (LE) | 60,440 | 60,440 | 60,440 | 60,440 | 60,440 | 60,440 |
| Speed Grade | I3 | C5 | I5 | C3 | C4 | I4 |
| Operating Temperature | -40°C to +100°C (Industrial) | 0°C to +85°C (Commercial) | -40°C to +100°C (Industrial) | 0°C to +85°C (Commercial) | 0°C to +85°C (Commercial) | -40°C to +100°C (Industrial) |
| Embedded Memory (bits) | 2,544,192 | 2,544,192 | 2,544,192 | 2,544,192 | 2,544,192 | 2,544,192 |
| DSP Blocks (18×18 Multipliers) | 36 (144) | 36 (144) | 36 (144) | 36 (144) | 36 (144) | 36 (144) |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
Key Differentiators
- Pin-compatible across the entire 672-ball EP2S60 family — easy speed/temp migration (vs EP2S60F672C5N)
- 60K LEs at industrial temperature — rare combination in 2008-era FPGA market (vs EP2S30F672I4N)
- Stratix II ALM fabric — 8 LUTs per ALM doubles effective logic density vs Stratix (vs Xilinx XC5VSX50T (Virtex-5 SXT))
Design Notes
Estimated: At typical utilization of 70% LEs at 50% toggle rate with 1.2 V core, the EP2S60F672I3N dissipates approximately 3–5 W of power. The 672-ball FC-FBGA has a theta_JA of approximately 8–10 C/W with a standard 4-layer JEDEC test board, giving a junction temperature rise of 25–50 C above ambient. For high-utilization industrial applications at 100 C ambient, additional thermal relief is required via thermal via arrays under the center balls and forced air cooling. Designers should compute actual T_j using the Quartus II PowerPlay early power estimator and confirm thermal margin per Altera Application Note AN358.
The 672-ball FC-FBGA uses 1.0 mm ball pitch, requiring a 4–6 layer PCB with 0.4–0.5 mm drilled microvias for BGA fanout. The Altera Stratix II Hardware Reference recommends a 1 oz copper ground plane directly under the BGA with thermal via arrays (0.3 mm vias on 1.2 mm grid) for heat dissipation. Differential LVDS pairs must be length-matched to within 150 ps for reliable 1 Gbps operation. Decoupling requires 0.1 μF, 1 μF, and 22 μF ceramic capacitors within 200 mils of each power pin per Altera AN358. The configuration EPCS flash should be within 4 inches of the FPGA to maintain signal integrity on the serial configuration bus.
Common pitfalls: (1) Quartus II toolchain confusion — designers sometimes attempt to use Quartus Prime, which does NOT support Stratix II. Stick with Quartus II 13.0sp1 with license renewal via the Altera Legacy Software portal. (2) Speed-grade ordering — the I3, I4, I5 grades differ in Fmax only, not in functionality; you can always substitute a faster grade. (3) Industrial vs Commercial temperature — the I3 device can be used in commercial temperature but not vice versa, per Altera datasheet. (4) Last-time-buy risk — execute lifetime buys of 3–5 years' supply for production designs; avoid new designs unless migration path is verified. (5) JTAG chain — use Altera USB-Blaster II with a 10-pin header per AN 39; the older ByteBlaster is unsupported.
Compliance Information
RoHS compliant per Altera/Intel product specifications. 672-ball FC-FBGA uses lead-free SAC405 solder balls per JEDEC J-STD-020. AEC-Q100 not applicable (FPGAs not in automotive qualified parts list — see Cyclone V or Arria for automotive). Tin-lead variant (NPB) available for military applications requiring SnPb balls.
