EP2S60F672C5NGA - 60K LEs Stratix II FPGA, 492 I/O, 672-FBGA
MPN: EP2S60F672C5NGA ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $145 | $14,500.00 |
| 500 | $128 | $64,000.00 |
| 1,000 | $115 | $115,000.00 |
EP2S60F672C5NGA Overview
A Field Programmable Gate Array (FPGA) is a reconfigurable semiconductor that lets engineers implement custom digital logic by programming an array of configurable logic blocks (CLBs), dedicated DSP blocks, embedded memory, and routing resources. Within the broader semiconductor taxonomy, an FPGA sits alongside ASICs and CPLDs as a programmable logic device (PLD), and Stratix II belongs to Intel's high-end performance FPGA family optimized for high logic density, embedded memory, and DSP throughput. This taxonomy places the EP2S60F672C5NGA in the integrated circuits > FPGA & CPLD category, serving applications where custom hardware acceleration is required without the NRE cost of an ASIC.
Key features of the EP2S60F672C5NGA include 60,440 logic elements organized into 3,022 logic array blocks (LABs), approximately 2,544,192 bits of total embedded RAM, dedicated DSP blocks for high-throughput arithmetic, and 492 user I/O pins supporting multiple I/O standards (LVDS, LVTTL, SSTL, HSTL). The 672-FBGA package exposes extensive I/O connectivity for memory interfaces and high-speed serial/parallel links. The C5 speed grade provides balanced timing margins for commercial applications, while the NGA variant supports a specific operating envelope required by OEMs.
Technically, Stratix II uses a 90 nm process with adaptive logic modules (ALMs) that improve logic utilization versus earlier architectures. The device integrates TriMatrix memory blocks, up to 12 global clock networks, and dedicated multiplier/adder DSP blocks for high-performance filtering and FFT operations. These architectural elements make the EP2S60F672C5NGA suitable for protocol bridging, high-speed image processing, and software-defined radio baseband designs.
Typical applications include high-end ASIC prototyping, telecommunications line-card processing, video broadcasting equipment, military/aerospace signal processing, and high-end test and measurement instrumentation. Engineers select this part when designs exceed the capacity of Cyclone II devices but do not require the larger Stratix II EP2S130/EP2S180 variants. The 672-FBGA package is the common platform for Stratix II devices, ensuring PCB layout reuse across the family.
Design consideration: Stratix II FPGAs require careful power-rail sequencing (1.15 V to 1.25 V core) and robust thermal management, since high logic utilization can exceed 10 W dissipation. Designers must follow Altera's Quartus II power estimator and place decoupling capacitors within the manufacturer's guidelines to avoid in-system jitter.
This page synthesizes distributor inventory, drop-in alternatives, and design notes not consolidated on the original Altera datasheet.
Drop-in alternatives for EP2S60F672C5NGA — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S60F672C5NGA (same form factor and footprint) — differing in Speed Grade, Package, RoHS Status, Operating Temperature, Operating Temperature Grade.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S60F672C5N
✅ Drop-In✓ In Stock
$170 / Unit
View Datasheet →EP2S60F672C5
✅ Drop-In✓ In Stock
$410.85 / Unit
View Datasheet →EP2S60F672C4N
✅ Drop-In✓ In Stock
$325 / Unit
View Datasheet →EP2S60F672C4
✅ Drop-In✓ In Stock
$1080 / Unit
View Datasheet →EP2S60F672C3NGA
✅ Drop-In✓ In Stock
$1150 / Unit
View Datasheet →EP2S60F672C3N
✅ Drop-In✓ In Stock
$1175 / Unit
View Datasheet →EP2S60F672C5NGA Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Series | Stratix II |
| Logic Elements (LEs) | 60,440 |
| Logic Array Blocks (LABs) | 3,022 |
| Total RAM Bits | 2,544,192 |
| User I/O Pins | 492 |
| Package Type | 672-Ball FBGA |
| Package Dimensions | 27 x 27 mm |
| Supply Voltage (Core) | 1.15 V to 1.25 V |
| Speed Grade | C5 |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +85C (commercial, NGA variant) |
| Part Status | Active (inventory limited) |
| RoHS Status | Compliant |
| Supplier Device Package | 672-FBGA (27x27) |
EP2S60F672C5NGA 672-fbga (27x27) Pin Configuration Guide
Pin configuration for EP2S60F672C5NGA (672-fbga (27x27) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S60F672C5NGA.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S60F672C5NGA is suitable for 6 applications: ASIC Prototyping and Emulation, Telecommunications Line-Card Processing, High-Speed Data Acquisition Systems, Software-Defined Radio (SDR) Baseband, Video Broadcasting and Image Processing, Military and Aerospace Signal Processing.
ASIC Prototyping and Emulation
The EP2S60F672C5NGA's 60,440 logic elements and 492 user I/O pins make it a strong fit for ASIC prototyping where designers emulate multi-million-gate ASIC designs before tape-out. With 2.5 Mbits of embedded RAM and dedicated DSP blocks, it handles large register-transfer-level designs for pre-silicon validation. Placed on a custom validation board with JTAG and high-speed memory interfaces, it offers 10-50x faster verification than software simulation. Designers value the Quartus II toolchain support and the 672-FBGA package's routing density for complex SoC bring-up, though they must monitor power consumption under heavy utilization.
Recommended
Telecommunications Line-Card Processing
Telecom line cards require deterministic multi-gigabit packet processing, making the EP2S60F672C5NGA well-suited for OC-192/STM-64 and 10G Ethernet framer designs. Its 492 I/O pins support multiple SFI-4.2 / XAUI interfaces, while dedicated DSP blocks enable forward error correction (FEC) and encryption acceleration. Placed between the network processor and the SERDES PHY, the device buffers traffic and performs protocol conversion. The 27x27 mm 672-FBGA package allows compact line-card layouts, though engineers must consider the high pin count for backplane routing and apply Altera's high-speed PCB guidelines.
Recommended
High-Speed Data Acquisition Systems
High-speed data acquisition systems use the EP2S60F672C5NGA to interface with multi-channel ADCs running at hundreds of MSPS, where the 492 user I/O pins accommodate LVDS ADC data buses and the embedded RAM buffers high-bandwidth sample streams. The DSP blocks execute real-time FIR filtering and channel interpolation, while the TriMatrix memory supports circular sample buffers. Deployed in oscilloscopes, radar digitizers, and medical imaging front-ends, it outperforms microcontrollers in raw throughput. The C5 speed grade provides sufficient timing margin for 200+ MHz internal logic, but designers should verify pin-to-pin timing against their ADC's data-rate requirements.
Recommended
Software-Defined Radio (SDR) Baseband
Software-defined radio baseband processing relies on the EP2S60F672C5NGA's DSP blocks to implement FFT, channelization, and modulation/demodulation in reconfigurable hardware. With 60,440 LEs and 2.5 Mbits of RAM, it can process multiple simultaneous LTE or WiMAX channels in parallel. The device interfaces with RF front-ends via LVDS or LVTTL, while high-speed transceivers handle baseband-to-host links. Engineers select this part over DSP microprocessors when low latency (<10 microsecond) is critical for closed-loop beamforming. Quartus II's DSP Builder accelerates model-based design, and the 672-FBGA package supports high-density I/O required for multi-antenna MIMO systems.
Recommended
Video Broadcasting and Image Processing
Broadcast video equipment uses the EP2S60F672C5NGA for real-time SD/HD/3G-SDI video processing, scaling, and overlay generation where the high I/O count supports multiple parallel video streams. Its embedded memory acts as frame buffers, while DSP blocks execute color-space conversion and deinterlacing. The device handles JPEG2000 or H.264 codec acceleration for contribution encoders. With 492 I/O pins, the 672-FBGA package interfaces with multiple video ADCs and DACs simultaneously. Engineers benefit from Quartus II's video IP cores, though they must manage the device's power budget carefully under continuous video throughput.
Recommended
Military and Aerospace Signal Processing
Defense and aerospace platforms use the EP2S60F672C5NGA for radar signal processing, electronic warfare, and secure communications where its high logic density supports real-time I/Q demodulation, pulse compression, and cryptographic acceleration. The 672-FBGA package's 27x27 mm footprint suits SWaP-constrained environments, and the commercial NGA variant is often paired with ruggedized carrier boards for harsh-environment deployment. Engineers value the Stratix II family's mature design tools and extensive IP ecosystem for rapid mission system development. When higher temperature grades are needed, designers migrate to EP2S60F672I5N or later Intel FPGA families with extended military screening.
Recommended
Recommended Products Summary
Engineering reference data for EP2S60F672C5NGA — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S60F672C5N | EP2S60F672C5 | EP2S60F672C4N | EP2S60F672C3NGA |
|---|---|---|---|---|---|
| Package | 672-FBGA (27x27 mm) | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same |
| Brand | Intel | Intel - same | Intel - same | Intel - same | Intel - same |
| Logic Elements | 60,440 | 60,440 | 60,440 | 60,440 | 60,440 |
| Speed Grade | C5 | C5 | C5 | C4 (slower) | C3 (slowest) |
| User I/O Pins | 492 | 492 | 492 | 492 | 492 |
| Total RAM Bits | 2,544,192 | 2,544,192 | 2,544,192 | 2,544,192 | 2,544,192 |
| Suffix Variant | NGA | N (lead-free) | Standard | N (lead-free) | NGA |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
| Unit Price (qty-1, USD) | ~$185 | ~$180 | ~$190 | ~$175 | ~$170 |
Key Differentiators
- Same die as standard EP2S60F672C5N with NGA customer-specific screening (vs EP2S60F672C5N)
- Faster C5 speed grade vs C3/C4 alternatives (vs EP2S60F672C3NGA)
- Same 672-FBGA footprint shared with all EP2S60F672 variants (vs EP2S60F484C5N)
Design Notes
Stratix II EP2S60 devices require sequenced power rails: 1.15-1.25 V VCCINT core, 2.5 V VCCPD, and 3.3 V VCCIO for I/O banks. Designers must follow Altera's recommended power-up sequence (VCCINT first, then VCCPD, then VCCIO) to avoid in-rush currents and configuration failures. Use the Stratix II PowerPlay Early Power Estimator before PCB layout to budget decoupling capacitance. Estimated: at 60,440 LEs with 60% utilization and 200 MHz toggle rate, core current may exceed 3 A requiring multi-phase VRM design.
The 672-FBGA 27x27 mm package has a theta_JA of approximately 14 C/W with appropriate thermal via array beneath the exposed pad. Under high-utilization DSP workloads, junction temperature can exceed 100 C without airflow. Design thermal vias on a 1.0 mm pitch grid through the BGA's land pattern, and consider a heatsink for >5 W sustained dissipation. Estimated: at 5 W dissipation in still air, junction rises ~70 C above ambient; with 200 LFM airflow, the rise drops to ~25 C.
The 672-FBGA's 1.0 mm ball pitch requires 4-layer PCB minimum with microvia stackups for breakout routing. Use buried vias for inner rows and place decoupling capacitors on the opposite side directly under the package. Maintain 50 ohm controlled impedance for high-speed LVDS pairs, and follow Altera's pinout guidelines to assign PLL clock pins to dedicated clock-capable I/O banks. Place configuration flash (EPCS) within 2 inches of the FPGA's active serial interface.
Common pitfalls include: (1) failing to assert nCONFIG during power-up, leaving the device unconfigured; (2) mixing 2.5 V and 3.3 V I/O standards on the same bank without proper VCCIO planning; (3) overlooking JTAG chain ordering when programming multiple devices in series; (4) exceeding absolute maximum junction temperature during in-system programming; and (5) using EP2S60F672C5NGA as a drop-in for EP2S90/EP2S130 parts - those have different bitstreams even when the package is similar.
Compliance Information
RoHS compliant per Altera/Intel product page. Lead-free N suffix variant available (EP2S60F672C5N). AEC-Q100 not applicable - this is an FPGA, not an automotive analog IC. For automotive applications, choose AEC-Q100 qualified Cyclone IV/V or later Intel FPGA families.
