EP2S90F780C5 - Stratix II FPGA, 90,960 LEs, 780-FBGA | Altera
MPN: EP2S90F780C5 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1611.14 | $1,611.14 |
| 5 | $1450 | $7,250.00 |
| 10 | $1320 | $13,200.00 |
| 25 | $1200 | $30,000.00 |
| 50 | $1100 | $55,000.00 |
EP2S90F780C5 Overview
A Field Programmable Gate Array (FPGA) is a semiconductor device whose digital logic, interconnect, and I/O behavior are defined by a user-supplied configuration bitstream rather than fixed at the fab. In the taxonomy of programmable logic, FPGAs sit above CPLDs (less dense, non-volatile) and below fixed-function ASICs, occupying the niche where high logic density, high I/O count, and rapid design iteration are required. The Stratix II family specifically targets high-performance DSP, communications, and signal-processing workloads through its adaptive logic modules (ALMs), TriMatrix embedded memory, and dedicated DSP blocks capable of 18x18 bit signed multiplies at hundreds of MHz.
Key features of the EP2S90F780C5 include 4,548 Logic Array Blocks (LABs) / Adaptive Logic Modules, twelve global clock networks, support for external memory interfaces such as DDR, DDR2, QDR, QDRII, and RLDRAM, high-speed transceivers are NOT integrated on this die (Stratix II GX is the transceiver variant), and configuration via passive serial, fast passive parallel, or JTAG modes. The device also includes four enhanced PLLs per device plus up to eight fast PLLs for fine-grained clock synthesis.
The Stratix II architecture uses 1.25 V core logic with dedicated 0.9 V and 1.2 V auxiliary rails, an on-chip voltage regulator for some variants, and supports hot-socketing for live insertion into backplanes. The 90 nm process node and nine-layer metal stack deliver high logic utilization at moderate static power; designers should still budget for dynamic power based on toggle rate, especially when driving wide external buses or memory interfaces.
Typical applications include high-performance digital signal processing (software-defined radio, baseband modems), wireline telecommunications line cards, video broadcast and image processing, military and aerospace digital processing, and ASIC prototyping. The 534 user I/O and 4.5 Mbit of embedded memory make the EP2S90 a good fit when algorithms need both on-chip storage and large numbers of external connections.
When designing with this part, plan power sequencing (1.25 V core before 2.5 V/3.3 V I/O), provide decoupling per the Altera Stratix II PowerPlay Design Guidelines, and verify signal-integrity on wide DDR2 buses using IBIS models. Quartus II is the supported development environment; modern Quartus versions retain Stratix II support through the device legacy policy.
This page synthesizes distributor pricing, same-package drop-in alternatives, and design notes for legacy inventory planning - information not consolidated on any single manufacturer or distributor page.
Drop-in alternatives for EP2S90F780C5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F780C5 (same form factor and footprint) — differing in Package, Logic Elements, RoHS Status, Family, Speed Grade.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S90F780C4
✅ Drop-In✓ In Stock
$3050 / Unit
View Datasheet →EP2S90F780C4N
✅ Drop-In✓ In Stock
$365 / Unit
View Datasheet →EP2S90F780C5N
✅ Drop-In✓ In Stock
$198 / Unit
View Datasheet →EP2S90F780I4N
✅ Drop-In✓ In Stock
$188 / Unit
View Datasheet →EP2S130F780C5
✅ Drop-In✓ In Stock
$2295 / Unit
View Datasheet →EP2S130F780C4
✅ Drop-In✓ In Stock
$6500 / Unit
View Datasheet →EP2S90F780C5 Maximum Ratings & Electrical Characteristics
| Series | Stratix II |
| Family | Stratix II FPGA |
| Logic Elements | 90,960 |
| Logic Array Blocks / ALMs | 4,548 |
| Embedded RAM (Total RAM Bits) | 4,520,488 |
| User I/O Pins | 534 |
| Core Voltage | 1.15 V to 1.25 V |
| Process Technology | 90 nm CMOS |
| Internal Operating Frequency (max) | 609.76 MHz |
| Package Type | 780-ball FC-FBGA (FineLine BGA) |
| Package Dimensions | 29 x 29 mm |
| Ball Pitch | 1.0 mm |
| Operating Temperature | 0 C to 85 C (Commercial) |
| Speed Grade | C5 |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs | 4 enhanced + up to 8 fast PLLs |
| RoHS Status | RoHS non-compliant (per alterachips listing) |
EP2S90F780C5 29 x 29 mm Pin Configuration Guide
Pin configuration for EP2S90F780C5 (29 x 29 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F780C5.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F780C5 is suitable for 6 applications: Software Defined Radio (SDR) Baseband, Telecommunications Line Cards, High-Performance Digital Signal Processing, Video Broadcast and Image Processing, ASIC Prototyping, Military and Aerospace Digital Processing.
Software Defined Radio (SDR) Baseband
The Altera EP2S90F780C5 fits software-defined radio baseband processing because its 90,960 logic elements and 4,520,488 embedded RAM bits support wide FFT/iFFT pipelines and channelizer filters at baseband sample rates. The 4,548 LABs and dedicated 18x18 multipliers in the Stratix II DSP blocks deliver 250+ MHz FIR filter throughput, which is sufficient for LTE, WiMAX, and proprietary narrowband waveforms. The 534 user I/O provide ample margin for parallel digital IF interfaces to ADC/DAC companion parts such as the AD9230 or AD9777, while the 12 global clock networks and 4 enhanced PLLs handle the multi-rate clocking typical of DDC/DUC chains. The device's external memory interfaces (DDR, DDR2, QDRII, RLDRAM) allow packet buffering and coefficient storage without external logic. Power consumption scales with toggle rate; designers should use the Altera PowerPlay tool to estimate junction temperature in sealed enclosures.
Recommended
Telecommunications Line Cards
The EP2S90F780C5 serves telecom line-card designs (OC-192/STM-64 framers, multi-service switches, packet processors) because of its 534 user I/O and flexible I/O bank architecture supporting LVDS, LVTTL, LVCMOS, HSTL, and SSTL standards. The 4.5 Mbit of TriMatrix embedded memory holds lookup tables and packet descriptors, while dedicated DDR2 controllers with up to 600 MHz performance interface to external TCAM/QDR memory for classification engines. The 90 nm Stratix II process provides deterministic timing closure for traffic-shaping pipelines and deep queue management. The 780-FBGA package's 1 mm ball pitch allows 4-6 layer PCB stack-ups without microvia, keeping line-card BOM cost manageable. Hot-socketing is supported per Altera's Stratix II handbook, enabling live insertion into ATCA/AdvancedTCA backplanes for service-provider deployments.
Recommended
High-Performance Digital Signal Processing
The EP2S90F780C5 is well matched to high-performance DSP subsystems because Stratix II's DSP blocks deliver 18x18 bit signed multiplication with optional 36-bit accumulation in a single cycle at 370+ MHz, achieving up to 28 GMACS. Combined with the 4.5 Mbit of embedded memory, the device implements multi-tap FIR filters, FFT butterflies, Reed-Solomon codecs, and radar pulse-compression correlators without external multipliers. The 90,960 logic elements are sufficient for medium-size video codecs (H.264 baseline at D1 resolution) or multi-channel audio processing. The 12 global clocks and 4 enhanced PLLs route independent sample-rate clocks to different DSP clusters, simplifying timing closure. Compared to discrete DSP processor clusters, the FPGA approach trades power efficiency for parallel throughput - typical Stratix II DSP designs draw 8-15 W at full DSP utilization.
Recommended
Video Broadcast and Image Processing
The EP2S90F780C5 supports broadcast video processing applications such as HD-SDI routing, multi-format up/down/cross conversion, and real-time image processing for medical imaging or machine vision. The 534 user I/O accommodate multiple 10-bit HD-SDI input channels at 1.485 Gbps each (using the FPGA's LVDS I/O with appropriate external CDR), and the 4.5 Mbit of embedded memory holds line buffers for deinterlacing and scaling. The Stratix II ALM architecture efficiently maps pixel-pipeline operators (alpha blending, color-space conversion, sharpening kernels), and the dedicated memory blocks double as wide line buffers without consuming logic. The 780-FBGA package's 1 mm pitch is compatible with standard 4-6 layer PCB processes used in broadcast equipment. For 4K or higher resolutions, designers should evaluate the larger EP2S130 or EP2S180 Stratix II die.
Recommended
ASIC Prototyping
The EP2S90F780C5 is commonly used as an ASIC prototyping vehicle because 90,960 logic elements and 4.5 Mbit of block RAM can map medium-complexity ASICs (consumer SoCs, peripheral controllers, communication ASSPs) at 1:1 gate equivalent for evaluation. The 780-ball FBGA package exposes 534 user I/O for bringing out ASIC pads, supporting split-prototype multi-FPGA partitioning when needed. The Quartus II design flow accepts standard HDL (Verilog, VHDL) and supports gate-level netlists from synthesis tools (Synopsys Design Compiler, Cadence RTL Compiler), enabling rapid ASIC-to-FPGA retargeting. The 90 nm process and 1.25 V core operate at speeds close to the target ASIC, so timing validation is meaningful. For larger ASICs (>2M gates), multiple EP2S90/EP2S130/EP2S180 devices are stacked on a multi-FPGA prototyping board.
Recommended
Military and Aerospace Digital Processing
The EP2S90F780C5 (in extended-temperature EP2S90F780I4N variant) supports military and aerospace digital processing where long-term component availability and radiation tolerance are required. While the standard EP2S90F780C5 is commercial-grade, the family has heritage in defense programs and is supported through Altera/Intel long-term supply contracts. The 780-FBGA package's 1 mm pitch accommodates ruggedized PCB stack-ups used in avionics and shipboard electronics, and the Stratix II architecture's deterministic timing is well-suited to safety-critical pipelines. Designers should evaluate the industrial-grade EP2S90F780I4N (-40 C to +100 C) for environments beyond commercial 0-85 C. For radiation-hardened designs, the Microsemi/RTAX family is preferred; the EP2S90F780C5 is best suited to sheltered airborne or ground-mobile applications with limited radiation exposure.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F780C5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F780C4 | EP2S90F780C4N | EP2S90F780C5N | EP2S90F780I4N | EP2S130F780C5 |
|---|---|---|---|---|---|---|
| Package | 780-FBGA (29x29) | 780-FBGA (29x29) - same | 780-FBGA (29x29) - same | 780-FBGA (29x29) - same | 780-FBGA (29x29) - same | 780-FBGA (29x29) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Logic Elements | 90,960 | 90,960 (same die) | 90,960 (same die) | 90,960 (same die) | 90,960 (same die) | 132,540 (+46%) |
| Embedded RAM | 4,520,488 bits | 4,520,488 bits | 4,520,488 bits | 4,520,488 bits | 4,520,488 bits | 6,747,840 bits (+49%) |
| Speed Grade | C5 (commercial) | C4 (faster) | C4 (faster) | C5 (same) | I4 (industrial) | C5 (same) |
| Operating Temperature | 0 C to 85 C (commercial) | 0 C to 85 C | 0 C to 85 C | 0 C to 85 C | -40 C to +100 C | 0 C to 85 C |
| User I/O | 534 | 534 | 534 | 534 | 534 | 534 |
| Pin Compatibility | 780-FBGA reference | Yes - bitstream-compatible | Yes - bitstream-compatible | Yes - bitstream-compatible | Yes - bitstream-compatible | PCB pin-compatible; recompile required |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
Key Differentiators
- Same 780-FBGA package and pinout as EP2S90F780C4 with faster speed grade (vs EP2S90F780C4)
- Same 780-FBGA footprint, larger 132,540-LE die (46% more logic) (vs EP2S130F780C5)
- Industrial temperature variant extends operating range to -40 C to +100 C (vs EP2S90F780I4N)
Design Notes
Power the EP2S90F780C5 with a 1.15-1.25 V core supply (VCCINT), a 2.5 V auxiliary (VCCAUX) for PLLs, and per-bank VCCIO for I/O. Per the Altera Stratix II handbook, VCCINT must reach 0.8 V before VCCIO ramps to prevent I/O latch-up; use a sequenced power controller such as the LTC2923 or ISL6236. Decoupling requires 100 nF X7R capacitors within 100 mils of every power pin plus 10 uF bulk caps per supply rail. Estimated quiescent current for an unconfigured EP2S90F780C5 is around 1.5 A on VCCINT; configured designs can draw 3-6 A on VCCINT plus 0.5-1.5 A per VCCIO bank. The 90 nm Stratix II die does not include an on-die voltage regulator, so the discrete regulator must provide tight load-line regulation under dynamic transients.
Estimated: at 85% logic utilization and 100 MHz toggle rate, the EP2S90F780C5 dissipates 8-12 W on VCCINT alone. The 780-FBGA package (29x29 mm) with 1 mm pitch requires 4-6 layer PCB with continuous ground and power planes directly under the BGA to spread heat. For full-power designs, the 780-FBGA's theta_JA is approximately 14 C/W with a 4-layer JEDEC test board; without thermal vias under the package, junction temperature can exceed 100 C in 25 C ambient. Use the Altera PowerPlay Early Power Estimator before PCB layout to size the thermal solution. Commercial 0-85 C ambient assumes a moderate airflow or heatsink - sealed enclosures should use the industrial I4N variant or derate clock rates.
Use 0.5 oz copper outer layers and 1 oz inner layers with 4 mil dielectric thickness for the 780-FBGA. The 1 mm BGA pitch requires 12-16 mil dog-bone fanout or via-in-pad microvia stack-ups. Route all 12 global clock signals on inner stripline layers with 50 ohm controlled impedance, and keep all DDR/DDR2 DQS-DQ groups within 25 mil length-match per the Altera External Memory Interface Handbook. The 534 user I/O at LVDS 1.25 Gbps require 100 ohm differential routing and AC-coupling caps near the receiver. Place configuration PROM (EPCS16 or EPCS64) within 2 inches of the FPGA's active serial pins to avoid signal-integrity issues during configuration. JTAG chain must include the 10 kohm pull-up on TCK and TMS per IEEE 1149.1.
Do not confuse the EP2S90F780C5 (Stratix II, no transceivers) with the EP2SGX90F (Stratix II GX, with transceivers) - they are NOT pin-compatible despite the similar naming. The 'C5' speed grade is the slower bin; C6/C7 are even slower but less common, and C4 is faster. The N suffix denotes lead-free finish per JEDEC J-STD-609 - both C5 and C5N share the same die and pinout, but some contract manufacturers require the N variant. Do not attempt to migrate bitstreams between Stratix II (this part) and Cyclone II/IV or Stratix III/IV without recompiling in Quartus II - the ALM, memory block, and PLL architectures are incompatible. The MSL rating for FBGA packages is typically MSL3, so pre-bake before reflow if the bag has been open more than 168 hours.
Compliance Information
RoHS non-compliant per alterachips.com listing (status as of 2026-09-09). Lead-free N-suffix variants (EP2S90F780C5N) are available for RoHS-compliant builds. REACH, halogen-free, and conflict-minerals status not reported in the verified web data and should be requested from Altera/Intel directly. AEC-Q100 is not applicable - this is an FPGA, not an automotive-grade IC; FPGAs are qualified per their own Altera/Intel quality flow.
