EP2S90F780C5N - Stratix II FPGA, 90K LE, 780-FBGA | Intel
MPN: EP2S90F780C5N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $268.5 | $2,685.00 |
| 25 | $252 | $6,300.00 |
| 100 | $225 | $22,500.00 |
| 500 | $198 | $99,000.00 |
EP2S90F780C5N Overview
What is an FPGA? A Field-Programmable Gate Array is a semiconductor integrated circuit composed of configurable logic blocks (CLBs), programmable interconnects, and dedicated silicon resources such as block RAM, DSP blocks, and high-speed transceivers. FPGAs sit above general-purpose microcontrollers in the digital design hierarchy: they can implement arbitrary parallel logic, custom processor cores, hardware accelerators, and high-bandwidth data-path pipelines that an ASIC would otherwise handle, but with the advantage of in-system reprogrammability. The Stratix II family in particular pioneered the adaptive logic module (ALM) architecture, replacing the traditional 4-input LUT with an 8-input fracturable LUT for higher logic efficiency.
Key features of the EP2S90F780C5N include up to 534 user I/O pins, embedded multiplier blocks suitable for DSP, dedicated high-speed serial interfaces, and support for external memory interfaces including DDR, DDR2, QDR, and RLDRAM. The device integrates PLLs for clock management and offers robust configuration options through JTAG, Passive Serial, Fast Passive Parallel, and Active Serial modes.
Architecturally, the Stratix II ALM can implement any 7-input LUT plus a small auxiliary function, dramatically reducing logic-area waste compared to older 4-LUT architectures. TriMatrix embedded memory blocks (M512, M4K, M-RAM) provide distributed RAM, ROM, FIFO, and shift-register functions, while DSP blocks deliver dedicated multiply-accumulate throughput. The 90 nm process, 1.2 V core, and 1.0 V/1.2 V selectable I/O standards balance performance and power.
Typical applications include telecommunications baseband processing, high-speed image and video processing, ASIC prototyping, military and aerospace signal processing, and industrial control systems. With 534 I/O and ~4.5 Mbit of block RAM, the EP2S90F780C5N handles large data-plane buffers and multiple parallel interfaces.
Design consideration: Stratix II devices are now in their mature lifecycle. Designers targeting new designs should verify availability and consider Cyclone IV/V or MAX 10 as modern, lower-cost alternatives where the EP2S90's logic density is not required.
This page synthesizes distributor pricing, drop-in alternatives from the Site MPN list, lifecycle guidance, and practical design notes not consolidated in the manufacturer datasheet alone.
Drop-in alternatives for EP2S90F780C5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F780C5N (same form factor and footprint) — differing in Package, RoHS Status, Speed Grade, Operating Temperature, Logic Elements.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S90F780C5
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1100 / Unit
View Datasheet →EP2S90F780C4N
✅ Drop-In✓ In Stock
$365 / Unit
View Datasheet →EP2S90F780C4
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$3050 / Unit
View Datasheet →EP2S130F780C5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$2150 / Unit
View Datasheet →EP2S130F780C5
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$2295 / Unit
View Datasheet →EP2S90F780C5N Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements | 90,960 |
| Adaptive Logic Modules (ALMs) | 45,960 |
| Embedded Memory Bits | 4,520,488 |
| Embedded Multipliers (18x18) | 384 |
| Maximum User I/O | 534 |
| Process Technology | 90 nm CMOS |
| Core Supply Voltage | 1.2 V |
| Internal Frequency (max) | 609.76 MHz |
| Operating Temperature Range | 0C to 85C (TJ, commercial) |
| Speed Grade | C5 |
| Package | 780-ball FBGA, 29 x 29 mm, 1.0 mm pitch, lead-free |
| Mounting Type | Surface Mount |
| Configuration Method | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| RoHS Status | Lead-free (per datasheets.com listing) |
EP2S90F780C5N 780-ball fbga, 29 x 29 mm, 1.0 mm pitch, lead-free Pin Configuration Guide
Pin configuration for EP2S90F780C5N (780-ball fbga, 29 x 29 mm, 1.0 mm pitch, lead-free package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F780C5N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F780C5N is suitable for 6 applications: Telecommunications Baseband Processing, ASIC Prototyping and Emulation, High-Speed Image and Video Processing, Military and Aerospace Signal Processing, Industrial Control and Test Instrumentation, Software-Defined Radio (SDR) Platforms.
Telecommunications Baseband Processing
The EP2S90F780C5N fits telecom baseband designs because of its 90,960 logic elements and 384 embedded 18x18 multipliers, which deliver the parallel multiply-accumulate throughput needed for channelization, FEC decoding, and baseband demodulation. The 4.52 Mbit of TriMatrix block RAM buffers symbol-rate data across multiple antenna streams while the 534 user I/O mates to external DDR/QDR memories and high-speed ADCs/DACs. Designers benefit from Quartus II's pre-verified DSP Builder IP cores for FFTs, Viterbi, and Turbo decoders that target Stratix II silicon.
Recommended
ASIC Prototyping and Emulation
With 90,960 logic elements and 4.52 Mbit of embedded memory, the EP2S90F780C5N acts as a multi-million-gate ASIC prototyping vehicle, partitioning large SoC designs across multiple FPGAs via TDM or HTILE-style logic-sharing interfaces. Its 780-ball FBGA exposes 534 user I/O, which supports enough off-chip bandwidth to maintain real-time verification of CPU cores, peripherals, and memory subsystems. Quartus II's TimeQuest timing analyzer and incremental compile flow let design teams iterate the prototype quickly, while the Stratix II ALM preserves high logic utilization compared to 4-LUT families.
Recommended
High-Speed Image and Video Processing
The EP2S90F780C5N supports real-time HD video pipelines because its 534 user I/O and TriMatrix memory deliver the bandwidth needed for multi-channel Camera Link, LVDS, or HDMI ingest, while the 384 DSP blocks accelerate 2D convolution, Sobel edge detection, and motion-estimation kernels at full frame rate. Designers use parallel pixel pipelines across the ALM fabric, distributing frame buffers across M4K and M-RAM blocks to avoid off-chip memory bottlenecks. Quartus II's Video and Image Processing (VIP) suite provides ready-made IP for color space conversion, scaling, and deinterlacing that maps directly to the ALM and DSP resources.
Recommended
Military and Aerospace Signal Processing
The EP2S90F780C5N's commercial 0-85C range can be extended via the EP2S90F780I5N industrial-grade counterpart for ruggedized signal-processing applications in radar, electronic warfare, and avionics where MIL-STD-810 environmental qualification is required. The 90K LE capacity and 384 DSP blocks enable pulse-compression, beamforming, and synthetic-aperture-radar (SAR) back-projection at real-time rates, while the lead-free FBGA withstands typical aerospace reflow profiles. Designers use the Stratix II hardened PCI Express and SERDES blocks to feed digitized antenna arrays back to mission processors.
Recommended
Industrial Control and Test Instrumentation
The EP2S90F780C5N suits industrial test and measurement platforms because its parallel logic and high I/O count allow simultaneous control of multi-axis motor drivers, simultaneous sampling of ADC channels, and real-time computation of control loops in PLLs and DSP blocks. The 4.52 Mbit of embedded RAM holds real-time waveform captures and PID coefficients without external memory, while the 780-BGA provides sufficient I/O for parallel bus interfaces to legacy industrial peripherals. Quartus II's Nios II soft-core lets designers integrate a processor for supervisory control on the same fabric.
Recommended
Software-Defined Radio (SDR) Platforms
The EP2S90F780C5N is well-matched to wideband SDR front-ends because its 384 18x18 multipliers and TriMatrix block RAM implement multi-rate FIR filtering, digital down/up-conversion, and channelizer polyphase filterbanks in real time at sample rates up to hundreds of MSPS. The 534 user I/O accommodates parallel LVDS ADC/DAC interfaces, while the dedicated PLLs provide multiple synchronized sample clocks for MIMO architectures. Designers can pair the FPGA with RF tuners and use Quartus II DSP Builder to generate fixed- or floating-point datapaths that exploit the Stratix II DSP block architecture efficiently.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F780C5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F780C5 | EP2S90F780C4N | EP2S90F780C4 | EP2S130F780C5N | EP2S130F780C5 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 780-ball FBGA, 29x29 mm, 1.0 mm pitch | 780-ball FBGA - same | 780-ball FBGA - same | 780-ball FBGA - same | 780-ball FBGA - same | 780-ball FBGA - same |
| Family | Stratix II | Stratix II | Stratix II | Stratix II | Stratix II | Stratix II |
| Logic Elements | 90,960 | 90,960 - same | 90,960 - same | 90,960 - same | 132,540 (+46%) | 132,540 (+46%) |
| Embedded Memory | 4,520,488 bits | 4,520,488 bits - same | 4,520,488 bits - same | 4,520,488 bits - same | 6,747,840 bits (+49%) | 6,747,840 bits (+49%) |
| Speed Grade | C5 | C5 - same | C4 (slower ~10-15%) | C4 (slower ~10-15%) | C5 - same | C5 - same |
| Embedded 18x18 Multipliers | 384 | 384 - same | 384 - same | 384 - same | 504 (+31%) | 504 (+31%) |
| Operating Temperature | 0C to 85C (commercial) | 0C to 85C - same | 0C to 85C - same | 0C to 85C - same | 0C to 85C - same | 0C to 85C - same |
| Lead-Free (N suffix) | Yes | No (SnPb finish) | Yes | No (SnPb finish) | Yes | No (SnPb finish) |
Key Differentiators
- Higher-density drop-in on same 780-BGA footprint (vs EP2S90F780C4N)
- Faster speed grade over C4 equivalent (vs EP2S90F780C4N)
- Lead-free finish for RoHS/automotive compliance (vs EP2S90F780C5 (no 'N' suffix))
Design Notes
The 780-ball FBGA at 1.0 mm pitch has a relatively high junction-to-ambient thermal resistance; for sustained high-utilization designs (above ~70% logic utilization at 200+ MHz), design 4+ thermal vias under the central BGA ball grid and at least 8 thermal vias directly beneath the die flag. Stratix II power can exceed 10 W under full DSP load - consider forced airflow or a heatsink attached with thermal interface material. Junction temperature must remain below 85C for the commercial-grade EP2S90F780C5N; use the EP2S90F780I5N for industrial deployments.
A 1.0 mm pitch FBGA requires a multilayer PCB stack-up with HDI microvias or via-in-pad construction for reliable assembly. Recommended stack-up: 8+ layers with 0.5 oz copper outer / 1 oz copper inner, FR-4 high-Tg (Tg >=170C) dielectric, and ENIG surface finish. Use a 4-6 mil BGA pad diameter with solder mask-defined (SMD) pads to reduce bridging risk. Reference Intel AN 224 'Stratix II Board Design Guidelines' for detailed escape routing recommendations.
Stratix II PLLs require clean, isolated power (VCCA_PLL) with a pi-filter (ferrite bead + decoupling caps) and a dedicated ground island connected to the main ground plane at a single point. Place differential clock inputs (CLK[0..15]) within the dedicated clock input region with matched-length, 50 ohm impedance-controlled traces; keep these traces far from switching I/O to avoid coupling. Dedicated configuration pins (nCONFIG, nSTATUS, CONF_DONE) must be pulled to their idle states per the configuration scheme chosen in Quartus II Device & Pin Options.
Estimated: this part is marked Obsolete as of 2026-09-09 per the GlobalSpec distributor database - do not commit new high-volume production designs to it. Verify all Stratix II configurations, JTAG IDs, and pinout files in Quartus II v13.1 (the last officially supported IDE for Stratix II); do not use newer Quartus versions, which drop legacy device support. When migrating to Stratix IV or Cyclone V, be aware that ALM-to-LAB mapping and DSP block architectures differ - recompile all IP cores and re-validate timing closure.
Compliance Information
RoHS compliance per datasheets.com listing (lead-free 'N' suffix). REACH, halogen-free, and conflict-minerals status not stated in the verified web data; AEC-Q100 not applicable for FPGAs.
