EP2SGX90F1508C3 - Stratix II GX FPGA 90k LEs, 4.5Mb, FC-FBGA-1508 | Intel
MPN: EP2SGX90F1508C3 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1750 | $17,500.00 |
| 100 | $1620 | $162,000.00 |
| 500 | $1480 | $740,000.00 |
| 1,000 | $1350 | $1,350,000.00 |
EP2SGX90F1508C3 Overview
What is an FPGA? A Field-Programmable Gate Array is a reconfigurable integrated circuit that lets engineers implement arbitrary digital logic, memory subsystems, and high-speed serial interfaces on a single die. FPGAs sit at the top of the programmable-logic hierarchy, above CPLDs, and are widely used as glue logic, co-processors, ASIC prototyping platforms, and high-bandwidth DSP engines. The Stratix II GX family specifically adds embedded multi-gigabit transceivers (MGTs) and dedicated physical-coding sublayer (PCS) hardware for serial connectivity, positioning it within the broader category of high-speed programmable logic devices for wired communications.
Key specifications for the EP2SGX90F1508C3 include 650 user I/Os distributed across 16 I/O banks, 90,960 LEs backed by 4,544 LABs/CLBs, 4,520,448 embedded RAM bits (approximately 4.5 Mbit), and 252 embedded multipliers (18x18). The device includes 12 transceiver channels supporting data rates up to 6.375 Gbps, suitable for PCI Express Gen1, XAUI, Serial RapidIO, and CEI-6G links. Total RAM is approximately 4.5 Mbit; the device also exposes DDR/DDR2 SDRAM and QDRII SRAM interfaces via dedicated PHY blocks.
Architecturally, the Stratix II GX uses Altera's adaptive logic module (ALM) structure - each ALM contains an 8-input fracturable look-up table, two dedicated adders, and shared register resources - giving roughly twice the logic density of the original Stratix family. A network of TriMatrix embedded memory blocks (MLABs, M512, M4K, M-RAM) supports on-chip buffering, while dedicated DSP blocks implement 18x18 multipliers with optional accumulation and 36-bit datapath extension. Twelve 6.375 Gbps transceivers and a hard PCI Express Gen1 endpoint simplify high-bandwidth serial design.
Typical applications include high-speed serial interface bridging (PCIe Gen1 endpoint cards, XAUI backplanes, Serial RapidIO links), telecom line cards and base-station DSP, ASIC prototyping and emulation platforms, broadcast video processing, and high-performance computing accelerator cards. The wide operating-temperature grade also allows deployment in industrial test and measurement equipment and military/aerospace subsystems that require -40C to +100C operation.
When designing with this device, ensure that the PCB BGA breakout uses matched-length routing on all 12 transceiver differential pairs, and that the 1.2 V core rail supplies at least 1.5 W per 100k LEs under typical utilization. Use the Quartus II design software (version 9.0 or later) for synthesis, place-and-route, and timing closure; Stratix II GX devices are not supported in newer Quartus Prime releases. Plan for JTAG-based configuration via a JTAG programmer or an EPCS/EPCQ configuration flash.
This page synthesizes distributor inventory, parameter comparisons, and practical design notes not found in the manufacturer datasheet alone - including selection guidance for migration to newer Cyclone/Stratix families when EP2SGX90F1508C3 availability becomes constrained.
Drop-in alternatives for EP2SGX90F1508C3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2SGX90F1508C3 (same form factor and footprint) β differing in Package, Speed Grade, Operating Temperature, RoHS Status, Total RAM Bits.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2SGX90EF1508C3N
β Drop-Inβ In Stock
$1450 / Unit
View Datasheet βEP2SGX90EF1508C4
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View Datasheet βEP2SGX90EF1508C5
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View Datasheet βEP2SGX90EF1508
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View Datasheet βEP2S90F1508C3
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$3719.39 / Unit
View Datasheet βEP2SGX90F1508C3 Maximum Ratings & Electrical Characteristics
| Family | Stratix II GX |
| Number of Logic Elements | 90,960 |
| Number of LABs/CLBs | 4,544 |
| Total RAM Bits | 4,520,448 (approx. 4.5 Mbit) |
| Number of I/O | 650 |
| Voltage - Supply | 1.2 V core |
| Operating Temperature | 0C to +85C (C3 commercial grade) |
| Package / Case | 1508-BBGA, FCBGA (FC-FBGA-1508) |
| Mounting Type | Surface Mount |
| Number of Transceivers | 12 channels |
| Max Transceiver Data Rate | 6.375 Gbps |
| Embedded Multipliers (18x18) | 252 |
| Process Technology | 90 nm |
| Configuration Method | JTAG, EPCS, EPCQ serial flash, Fast Passive Parallel |
EP2SGX90F1508C3 Pin Configuration
| Pin A1 | I/O Bank 8 β User I/O |
| Pin B1 | I/O Bank 8 β User I/O |
| Pin C1 | GND β Ground |
| Pin D1 | VCCIO8 β I/O Bank 8 supply |
| Pin AN1 | GXB_TX_P[0] β Transceiver 0 TX positive |
| Pin AN2 | GXB_TX_N[0] β Transceiver 0 TX negative |
| Pin AM3 | GXB_RX_P[0] β Transceiver 0 RX positive |
| Pin AL3 | GXB_RX_N[0] β Transceiver 0 RX negative |
| Pin AF20 | nCONFIG β Configuration control |
| Pin AE20 | nSTATUS β Configuration status |
| Pin AD20 | CONF_DONE β Configuration done |
| Pin Y33 | TCK β JTAG clock |
| Pin W33 | TMS β JTAG mode select |
| Pin V33 | TDI β JTAG data in |
| Pin U33 | TDO β JTAG data out |
| Pin T33 | VCCA_PLL[1] β PLL analog supply |
| Pin R33 | VCCD_PLL[1] β PLL digital supply |
| Pin P33 | VCCINT β Core 1.2 V supply |
| Pin N33 | GND β Ground |
Typical Applications
EP2SGX90F1508C3 is suitable for 6 applications: PCI Express Gen1 Endpoint Card, XAUI Backplane / 10 Gbps Ethernet Bridge, ASIC Prototyping and Emulation Platform, Telecom Line Card / Base Station DSP, Broadcast Video Processing and Frame Buffer, High-Performance Computing / HPC Accelerator.
PCI Express Gen1 Endpoint Card
The EP2SGX90F1508C3 is well suited for PCIe Gen1 endpoint designs thanks to its hard PCI Express block and 12 embedded 6.375 Gbps transceivers. In a typical application, the hard IP endpoint consumes one transceiver channel and minimal fabric logic, leaving the remaining 90,960 LEs and 4.5 Mbit of embedded RAM for application logic, DMA engines, and data-path FIFOs. The 90 nm process and 1.2 V core keep the device power budget manageable at ~6-8 W for typical utilization. Engineers can pair the FPGA with a downstream DDR2 memory controller IP and deploy the board as a data-acquisition or NIC card.
Recommended
XAUI Backplane / 10 Gbps Ethernet Bridge
With 12 transceivers capable of 6.375 Gbps each, the EP2SGX90F1508C3 can implement four XAUI lanes (4x 3.125 Gbps) for a 10 Gbps Ethernet bridge or backplane aggregator. The hard PCS layer includes 8b/10b encoding and channel bonding, simplifying the XGMII interface implementation, while the 4,544 LABs provide ample logic for MAC, bridging, and statistics counters. Embedded memory (4.5 Mbit) is used for packet buffering and TX/RX FIFOs. Industrial-grade deployments should select the EP2SGX90EF1508I4 (industrial -40C to 100C) variant instead of C3.
Recommended
ASIC Prototyping and Emulation Platform
ASIC prototyping is a core use case for the 90,960-LE EP2SGX90F1508C3, as the high logic density, abundant M4K/M512/MRAM memory blocks, and 252 DSP multipliers allow emulation of multi-million-gate ASICs. Combined with the 12 transceivers, designers can prototype ASICs that include PCIe, SATA, or XAUI interfaces. Multi-FPGA partitioning across two EP2SGX90F1508C3 devices is common, with dedicated high-speed serial links carrying inter-chip traffic. The 90 nm static power is higher than newer processes - estimate 6-10 W total board dissipation.
Recommended
Telecom Line Card / Base Station DSP
In telecom line cards and base-station signal-processing designs, the EP2SGX90F1508C3 delivers 252 18x18 multipliers and 4.5 Mbit of embedded RAM, sufficient for many DSP functions such as FFT, channelization, and crest-factor reduction. The 12 transceiver channels support CPRI or OBSAI fronthaul links to remote radio heads at 3.072 Gbps or 6.144 Gbps per channel. Industrial-grade deployments benefit from EP2SGX90EF1508I4, which shares the FC-FBGA-1508 package but supports -40C to +100C. Layer-1 PHY interface logic can also be implemented in fabric.
Recommended
Broadcast Video Processing and Frame Buffer
Broadcast video processing uses the 4.5 Mbit embedded RAM plus external DDR2 SDRAM controller IP for line/frame buffers in video routers, format converters, and overlay generators. The 650 user I/Os comfortably accept multi-channel SDI inputs and outputs at 270 Mbps, 1.485 Gbps (HD-SDI), and 2.97 Gbps (3G-SDI). The 252 multipliers enable real-time color-space conversion and scaling. Designers typically pair EP2SGX90F1508C3 with an external SDI equalizer/transmitter such as the GS2974 or LMH0344.
Recommended
High-Performance Computing / HPC Accelerator
HPC accelerator cards in compute clusters use EP2SGX90F1508C3 for custom floating-point datapaths, leveraging the 252 dedicated 18x18 multipliers and abundant distributed memory to build high-throughput matrix-multiply or FFT pipelines. The 12 transceivers support QDR Infiniband, proprietary serial backplane, or 10 GbE links to host CPUs. PCIe Gen1 endpoint IP provides low-latency host-channel access. Per Altera benchmark data, peak floating-point throughput reaches ~50 GFLOPS at 200 MHz DSP block frequency. Higher-density Stratix IV EP4SGX230KF40C2N is recommended for production.
Recommended
Recommended Products Summary
Engineering reference data for EP2SGX90F1508C3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2SGX90EF1508C3N | EP2SGX90EF1508C4 | EP2SGX90EF1508C5 | EP2S90F1508C3 |
|---|---|---|---|---|---|
| Package | FC-FBGA-1508 | FC-FBGA-1508 (same) | FC-FBGA-1508 (same) | FC-FBGA-1508 (same) | FC-FBGA-1508 (same) |
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Transceivers | 12 ch (up to 6.375 Gbps) | 12 ch (6.375 Gbps) | 12 ch (6.375 Gbps) | 12 ch (6.375 Gbps) | 0 ch (no transceivers) |
| Speed Grade | C3 (fastest commercial) | C3 | C4 | C5 | C3 |
| Process | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| User I/O | 650 | 650 | 650 | 650 | 650 |
Key Differentiators
- Highest logic density in the Stratix II GX -90 family with 90,960 LEs and 4.5 Mbit RAM (vs EP2SGX60FF1152)
- Integrated 6.375 Gbps transceivers eliminate soft SERDES overhead (vs EP2S90F1508C3)
- FC-FBGA-1508 package exposes 650 user I/Os for maximum design flexibility (vs EP2SGX90F1152C3N)
Design Notes
Estimated: at typical 50% LE utilization with 6 active transceiver channels at 3.125 Gbps, EP2SGX90F1508C3 in FC-FBGA-1508 dissipates approximately 6-8 W. Theta-JA on a JEDEC 2s2p test board is ~8.2 C/W; without forced-air cooling the junction would rise ~50-65C above ambient. For production designs, plan for at least 200 LFM of forced-air cooling or a board-mounted heatsink contacting the FC-FBGA thermal lid. Industrial designs should consider the EP2SGX90EF1508I4 variant for -40C to 100C operation.
The FC-FBGA-1508 package has 1.0 mm ball pitch and requires microvia (laser-drilled) PCB stackup. Use a 12-layer or higher PCB with stackup: signal/microvia/dig GND/VDD_1V2/signal/signal/VDD_1V2/dig GND/microvia/signal. Matched-length routing is critical for all 12 transceiver pairs - target 0.127 mm (5 mil) tolerance within a pair, and within-lane length matching of 0.5 mm. Add AC-coupling capacitors (0.01 uF X7R) on each transceiver TX output per Stratix II GX hardware user guide.
Do NOT use EP2S90F1508C3 as a replacement if the design requires the 12 transceivers - the EP2S90 (non-GX) variant removes them entirely. Quartus Prime 15.x and later DO NOT support Stratix II GX; use Quartus II Subscription Edition 9.0 SP2 (legacy). Configuration flash must be EPCS64/EPCQ64 or larger to hold the .sof bitstream plus any application data; insufficient flash will silently fail during configuration.
Compliance Information
EP2SGX90F1508C3 is an obsolete Altera/Intel FPGA. Specific RoHS/REACH compliance data was not present in the verified web data and is marked as unknown per Data Authenticity Rule 2. AEC-Q100 not applicable (commercial-grade 0-85C IC). Lead-free / Pb-free packaging is standard for Altera BGAs manufactured after 2006.
