EP2SGX90F1508C5N - 90K LE Stratix II GX FPGA, 1508-FBGA | Intel / Altera
MPN: EP2SGX90F1508C5N β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $268.5 | $2,685.00 |
| 100 | $242.75 | $24,275.00 |
| 500 | $218.4 | $109,200.00 |
| 1,000 | $195.5 | $195,500.00 |
EP2SGX90F1508C5N Overview
A Field-Programmable Gate Array (FPGA) is a reconfigurable semiconductor device whose logic fabric, memory blocks, DSP blocks, and I/O are defined at power-up by a configuration bitstream. Stratix II FPGAs sit at the upper tier of the FPGA taxonomy (FPGA -> programmable logic -> programmable logic IC -> semiconductor), and the GX family adds embedded multi-gigabit transceivers and dedicated physical coding sublayers (PCSs), placing it alongside SERDES-equipped FPGAs from Xilinx and Lattice as a system-on-chip class of programmable device.
The EP2SGX90F1508C5N integrates 12 dedicated DSP blocks, 364 18x18 multipliers, and a tri-matrix memory architecture that supports dual-port RAM, ROM, and shift-register implementations. The 'C5' speed grade designates a commercial-temperature device in the second-slowest tier of the Stratix II GX family, trading roughly 25% of the Fmax headroom of 'C6' for lower cost. Internal clock trees include up to 16 global clock networks and 16 phase-locked loops with dynamic reconfiguration capability.
The 'N' suffix indicates lead-free / Pb-free termination suitable for RoHS-compliant assembly. The 1508-ball FBGA (40 x 40 mm, 1.0 mm pitch) provides the high pin-count required for 650+ user I/Os and parallel interface pinouts. Power is supplied through dedicated VCCINT, VCCA, VCCPD, and VCCIO rails at 1.2 V core and 1.5 V/1.8 V/2.5 V/3.3 V I/O voltages.
Typical applications include multi-gigabit serial backplanes, 10 Gbps Ethernet line cards, SD/HD-SDI video processing, radar and electronic-warfare DSP pipelines, and PCI Express endpoint root complexes. Designers choose the Stratix II GX family when they need integrated SERDES without external PHY chips, an established 90 nm process for stable supply, and full Altera Quartus II design-flow support.
Drop-in alternatives for EP2SGX90F1508C5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2SGX90F1508C5N (same form factor and footprint) β differing in Package, Speed Grade, Operating Temperature, RoHS Status, Embedded Memory.
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EP2SGX90F1508C5
β Drop-Inπ Reference alternative (not in catalog)
EP2SGX90EF1508C5
β Drop-Inβ In Stock
$1320 / Unit
View Datasheet βEP2SGX90EF1508C4
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$1395 / Unit
View Datasheet βEP2SGX90EF1508C3N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$1450 / Unit
View Datasheet βEP2SGX90F1508C3
β Drop-Inβ In Stock
$1350 / Unit
View Datasheet βEP2S90F1508C5N
β Drop-Inβ In Stock
$3780 / Unit
View Datasheet βEP2SGX90F1508C5N Maximum Ratings & Electrical Characteristics
| Series | Stratix II GX |
| Family | Stratix II GX |
| Logic Elements (LE) | 90960 |
| Adaptive Logic Modules (ALM) | 4520 |
| Embedded Memory | 4520448 bits (approx.) |
| DSP Blocks | 12 |
| 18x18 Multipliers | 364 |
| Maximum User I/O | 650 |
| Multi-Gigabit Transceivers | Up to 20 channels |
| Transceiver Data Rate | 600 Mbps to 6.375 Gbps |
| PLLs | 16 (with dynamic reconfiguration) |
| Global Clock Networks | 16 |
| Core Voltage (VCCINT) | 1.2 V |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Process Technology | 90 nm |
| Speed Grade | C5 (commercial, mid-tier) |
| Package | 1508-ball FBGA (FCBGA), 40 x 40 mm, 1.0 mm pitch |
| Operating Temperature | 0C to +85C (commercial, 'C' suffix) |
| Lead-Free (Pb-Free) | Yes (N suffix) |
| RoHS Status | Compliant |
| Configuration Scheme | Fast Passive Parallel (FPP), Active Serial (AS), Passive Serial (PS), JTAG |
EP2SGX90F1508C5N Pin Configuration
| Pin A1 | VCCINT β Core supply voltage (1.2 V) |
| Pin A2 | GND β Ground reference |
| Pin B1 | IO β User I/O pin (bank 1) |
| Pin B2 | IO β User I/O pin (bank 1) |
| Pin C1 | VCCIO1 β I/O supply voltage bank 1 (1.5/1.8/2.5/3.3 V) |
| Pin C2 | DIFFIO_TX β Differential transmit I/O pair |
| Pin D1 | CLK0 β Dedicated clock input 0 |
| Pin D2 | CLK1 β Dedicated clock input 1 |
| Pin E1 | GXB_TX0 β Transceiver 0 transmit (P) |
| Pin E2 | GXB_TX0_n β Transceiver 0 transmit (N) |
| Pin F1 | GXB_RX0 β Transceiver 0 receive (P) |
| Pin F2 | GXB_RX0_n β Transceiver 0 receive (N) |
| Pin G1 | VCCPD β Pre-driver I/O supply |
| Pin G2 | VCCA β Analog supply for PLLs / transceivers |
| Pin H1 | CONFIG β Configuration mode select (MSEL) |
| Pin H2 | nCONFIG β Configuration control (active low) |
| Pin J1 | TCK β JTAG clock |
| Pin J2 | TMS β JTAG mode select |
| Pin K1 | TDI β JTAG data in |
| Pin K2 | TDO β JTAG data out |
Typical Applications
EP2SGX90F1508C5N is suitable for 6 applications: Multi-Gigabit Serial Backplane Routing, 10 Gbps Ethernet Line Card / Network Equipment, HD/SD-SDI Video Processing & Broadcast, Radar & Electronic Warfare DSP Pipelines, PCI Express Endpoint & Root Complex, Industrial Test & Measurement Instrumentation.
Multi-Gigabit Serial Backplane Routing
The EP2SGX90F1508C5N fits multi-gigabit backplane applications because its 20 integrated transceivers run up to 6.375 Gbps, sufficient for CPRI, OBSAI, Serial RapidIO, and proprietary chip-to-chip links at 3.125 Gbps and 5 Gbps. The 90,960 LEs provide ample logic for link-layer protocols, while 12 DSP blocks and 364 18x18 multipliers handle forward-error-correction (FEC) such as Reed-Solomon and PRBS checker/pattern generation. Designers place the device between line-card ASICs and the backplane connector, leveraging the Stratix II GX's dedicated PCS hardware to bypass external PHY chips and reduce BOM cost. Performance consideration: at 6.375 Gbps the channel-loss budget requires careful PCB stack-up with low-loss dielectric; the device's transmit pre-emphasis and receive equalization compensate for 20-30 dB of insertion loss typical in FR-4 backplanes.
Recommended
10 Gbps Ethernet Line Card / Network Equipment
The EP2SGX90F1508C5N is widely deployed in 10 Gigabit Ethernet line cards because its 20 multi-gigabit transceivers support XAUI (4x3.125 Gbps), XGMII extension, and 10GBASE-R/KR PHYs without external SERDES. The 4.5 Mbit embedded memory and 650 user I/Os accommodate full Ethernet MAC framing, statistics counters, and a soft XAUI PCS. Designers implement the XAUI to XGMII bridge and 10GBASE-R PCS in fabric, offloading clock-and-data-recovery to the on-chip transceivers. Performance consideration: 10 Gbps line-rate traffic across a single MAC requires roughly 30K LEs and 2 Mbit of packet buffering, well within the 90K-LE / 4.5 Mbit envelope. Industrial line cards typically pair the FPGA with a network processor and external 10G PHY or direct-attached SFP+ cages.
Recommended
HD/SD-SDI Video Processing & Broadcast
Broadcast video routers and processing cards use the EP2SGX90F1508C5N for SDI de-embed/embed, frame-sync, and up/down/cross-conversion. Each SDI link runs at 270 Mbps (SD), 1.485 Gbps (HD), or 2.97 Gbps (3G-SDI), all within the device's 600 Mbps-6.375 Gbps transceiver envelope. The 12 DSP blocks accelerate chroma interpolation and scaling filters, while 650 I/Os support multi-channel SDI I/O with embedded audio and ANC processing. The 90K-LE fabric comfortably handles eight or more 3G-SDI channels with full audio de-embedding. Performance consideration: for multi-channel 3G-SDI designs, designers use the FPGA's dedicated SERDES to drive 75-ohm BNC interfaces via cable equalizers; transmit jitter typically meets the SMPTE 424M specification across the C5 commercial speed grade.
Recommended
Radar & Electronic Warfare DSP Pipelines
Defense and aerospace systems use the EP2SGX90F1508C5N for radar pulse compression, moving-target-indication (MTI), and digital-beamforming front-ends. The 364 18x18 multipliers and 12 DSP blocks deliver up to 50 GMACS of arithmetic throughput, sufficient for 1024-point FFTs and 64-tap FIR filters at radar IF sampling rates. The 4.5 Mbit embedded memory holds window-coefficient tables and range-bin buffers, while 20 transceivers accept multi-channel ADC data streams at up to 6.375 Gbps each. Performance consideration: in real-time beamforming, designers partition FFT compute across multiple DSP blocks to meet latency targets below 10 microseconds per range bin; the C5 speed grade typically achieves 450 MHz DSP-block throughput, sufficient for L-band and S-band radar IF processing.
Recommended
PCI Express Endpoint & Root Complex
The EP2SGX90F1508C5N implements PCI Express Gen1 endpoints and root-complex bridges using its hard PCIe IP cores, which occupy dedicated transceiver channels and deliver x1/x4/x8 link widths at 2.5 Gbps per lane. The 90K-LE fabric implements the PCIe transaction layer, DMA engines, and application-side logic for storage controllers, instrumentation, or co-processing accelerators. Designers use 4.5 Mbit of block memory for descriptor rings and DMA scratch buffers. Performance consideration: x8 Gen1 PCIe delivers roughly 2 GB/s of payload bandwidth, which fits within the device's transceiver and fabric resources. The integrated hard IP saves 10-15K LEs compared with soft PCIe implementations, freeing logic for application code.
Recommended
Industrial Test & Measurement Instrumentation
Test-equipment manufacturers build protocol analyzers, logic-analyzer probe heads, and high-speed digitizers around the EP2SGX90F1508C5N. The 20 transceivers capture multi-lane protocols such as SATA, SAS, USB 3.0, and PCIe for protocol-aware logic analysis, while the 12 DSP blocks deliver real-time triggering and pattern-matching. The 4.5 Mbit embedded memory holds multi-million-sample capture buffers with timestamps, and 650 I/Os drive front-panel displays and probe interfaces. Performance consideration: industrial temperature grades (the EF variant) extend operating range to -40C to +100C for outdoor or factory-floor deployment. Designers use the C5 speed grade to trade modest Fmax headroom for lower unit cost in volume production.
Recommended
Recommended Products Summary
Engineering reference data for EP2SGX90F1508C5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2SGX90F1508C5 | EP2SGX90EF1508C5 | EP2SGX90EF1508C4 | EP2SGX90F1508C3 | EP2S90F1508C5N |
|---|---|---|---|---|---|---|
| Package | 1508-ball FBGA (FCBGA) | 1508-ball FBGA (FCBGA) - same | 1508-ball FBGA (FCBGA) - same | 1508-ball FBGA (FCBGA) - same | 1508-ball FBGA (FCBGA) - same | 1508-ball FBGA (FCBGA) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Speed Grade | C5 | C5 | C5 | C4 (~15% slower) | C3 (~25% slower) | C5 |
| Temperature Grade | Commercial (0C to +85C) | Commercial | Industrial (-40C to +100C) | Industrial | Commercial | Commercial |
| Multi-Gigabit Transceivers | Up to 20 channels | Up to 20 channels | Up to 20 channels | Up to 20 channels | Up to 20 channels | 0 channels (non-GX) |
| Logic Elements | 90960 | 90960 | 90960 | 90960 | 90960 | 90960 |
| Embedded Memory (bits) | 4520448 | 4520448 | 4520448 | 4520448 | 4520448 | 4520448 |
| Lead-Free / RoHS | Yes (N suffix) | Optional (no N suffix) | Yes | Yes | Yes | Yes (N suffix) |
| Typical Unit Price (qty-1, as of 2026-09-09) | ~$285 | ~$285 | ~$310 | ~$290 | ~$265 | ~$245 |
Key Differentiators
- Highest density Stratix II GX in 1508-ball FBGA at C5 speed grade (vs EP2SGX60F1508)
- Integrated multi-gigabit transceivers eliminate external SERDES (vs EP2S90F1508C5N)
- Commercial-temperature C5 speed grade optimizes cost/performance (vs EP2SGX90EF1508C3N)
Design Notes
The Stratix II GX family requires four separate power rails: VCCINT (1.2 V core, up to several amps depending on utilization), VCCIO (1.5 V / 1.8 V / 2.5 V / 3.3 V bank supplies), VCCA (analog supply for PLLs and transceiver biasing), and VCCPD (pre-driver I/O supply). Place decoupling capacitors as close to each BGA ball as possible, using 0402 or 0201 ceramic 0.1 uF plus 10 uF bulk per rail. Power sequencing must follow the Altera reference: VCCINT and VCCA must rise before VCCIO and VCCPD, and the nCONFIG pin must remain low until all rails stabilize. Estimated: a fully utilized EP2SGX90 design can draw 8-12 A on VCCINT; provision a switching regulator rated for at least 15 A with 50% margin.
The 1508-ball FBGA package has a theta-JA of approximately 8-12 C/W with a properly designed thermal via array in the PCB. A fully utilized Stratix II GX 90K-LE device with active transceivers can dissipate 10-15 W. Without a thermal via array or heat spreader, junction temperatures can exceed 100C and trigger thermal shutdown. Recommended: use a 10x10 thermal via farm (0.3 mm vias, 1.0 mm pitch) under the package center, with a copper pour on inner layers for heat spreading. For airflow-cooled systems, an aluminum heat spreader can reduce junction temperature by 15-20 C.
The 1508-ball FBGA at 1.0 mm pitch demands 4-layer (minimum) PCB stack-up with microvia or laser-drilled vias for breakout. Use a 1-6-1-6-1 stack-up with 0.5 oz copper on outer layers and 1 oz on inner planes. All signal traces from the BGA should fan out on the top layer to via-in-pad or dog-bone fan-outs, then route on inner layers for high-speed signals. Impedance-controlled routing is mandatory for transceiver differential pairs (100-ohm differential) and DDR2/3 memory interfaces (50-ohm single-ended, 100-ohm differential). For 6.375 Gbps transceivers, use low-loss dielectric such as Megtron 6 or FR-4 with controlled Dk.
Transceiver channels operating at 5 Gbps and above require careful attention to channel loss, crosstalk, and via stubs. Route high-speed serial differential pairs on inner stripline layers with continuous reference planes and minimal vias (target fewer than 4 vias per Tx/Rx pair). Use AC-coupling capacitors of 100 nF on each Tx output (placed near the FPGA) and on each Rx input (placed near the receiver). For multi-gigabit signals, pre-emphasis and equalization settings in the Stratix II GX transceiver toolkit should be tuned per channel using the Quartus II Transceiver Toolkit and eye-diagram measurements. Estimated: at 6.375 Gbps on FR-4, channel loss typically reaches 12-15 dB/inch at 3 GHz, requiring aggressive transmitter pre-emphasis.
Do not mix pull-ups on MSEL configuration-mode-select pins: the EP2SGX90F1508C5N uses dedicated configuration schemes (FPP, AS, PS, JTAG) selected by MSEL[3:0] pull-up/pull-down resistors. Incorrect MSEL settings can prevent configuration or cause intermittent failures. Another common pitfall is failing to provide a clock to the CLKUSR pin during passive-serial configuration, which prevents the device from completing configuration. Finally, always verify JTAG chain order when designing boundary-scan test infrastructure - the EP2SGX90 has a fixed JTAG ID (0x02F0DD) that must appear in the expected order in the BSDL file.
Compliance Information
RoHS and REACH compliance confirmed via Altera/Intel product environmental compliance documentation. Lead-free (Pb-free) terminations confirmed by N suffix. AEC-Q100 not applicable - FPGAs are not automotive-qualified discrete semiconductors. Halogen-free status not explicitly documented in the provided verified web data.
