EP2SGX90FF1508C3N - 90K LE Stratix II GX FPGA, 1508-FCBGA | Intel / Altera
MPN: EP2SGX90FF1508C3N β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1695 | $16,950.00 |
| 100 | $1520 | $152,000.00 |
| 500 | $1395 | $697,500.00 |
| 1,000 | $1295 | $1,295,000.00 |
EP2SGX90FF1508C3N Overview
A Field Programmable Gate Array (FPGA) is a semiconductor integrated circuit whose digital logic function is defined after manufacturing via a configuration bitstream loaded into on-chip SRAM. FPGAs sit at the top of the programmable-logic hierarchy alongside CPLDs and structured ASICs, and Stratix II GX specifically targets high-bandwidth serial I/O, DSP, and embedded-processing applications. The 'GX' suffix indicates hardened multi-gigabit transceivers (MGTs) - in Stratix II GX, the transceiver blocks reach data rates up to 6.375 Gbps, allowing the device to bridge parallel logic fabrics to high-speed serial links such as PCIe, Serial RapidIO, XAUI, and custom backplanes.
Key features of the EP2SGX90FF1508C3N include 90,960 logic elements (LEs), 4,520,448 bits of embedded block RAM, 384 (18x18) multipliers for DSP operations, 12 transceiver channels, 8 PLLs (4 fast + 4 enhanced), and 650 user I/Os distributed across 12 I/O banks supporting LVDS, LVTTL, LVCMOS, HSTL, and SSTL standards. The device operates across industrial temperature grades with commercial ('C') speed grade 3 silicon, balancing timing margin and cost for mainstream prototyping.
Architecturally, the Stratix II GX fabric uses Altera's adaptive logic module (ALM), which packs eight inputs into a LUT-based structure with associated arithmetic and register resources, delivering higher effective logic density than the classic 4-input LUT. The transceiver blocks embed physical coding sublayer (PCS) hard IP including 8B/10B encoding, rate matching, and word alignment, which is critical for protocol bridging. Clock management is built around hierarchical PLLs feeding a global clock network.
Typical applications include high-speed serial interface bridging (PCIe Gen1/Gen2 endpoint, XAUI, Serial RapidIO), telecom backplane aggregation, prototype ASIC verification, DSP co-processing for wireless baseband, and high-performance test-and-measurement equipment. The 'C3' speed grade (slower corner) and 1508-ball package make it the typical choice for cost-sensitive prototyping rather than production timing closure.
When designing with this part, ensure your PCB can handle the 40 x 40 mm FC-FBGA BGA land pattern with 1.0 mm pitch - this typically requires 6-8 layer stack-ups with microvia or via-in-pad technology. Decoupling must follow the Stratix II GX PDN guidance, with hundreds of ceramic capacitors distributed under and around the package. Because this is a 90nm, 1.2V-core legacy device from Altera (now Intel FPGA), plan for thermal management and verify long-term supply through franchised distributors.
Drop-in alternatives for EP2SGX90FF1508C3N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2SGX90FF1508C3N (same form factor and footprint) β differing in Package, Operating Temperature, Speed Grade, RoHS Status, Logic Array Blocks (LABs).
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EP2SGX90FF1508C3ES
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EP2SGX90F1508C3
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View Datasheet βEP2SGX90FF1508C3N Maximum Ratings & Electrical Characteristics
| Family | Stratix II GX |
| Logic Elements (LEs) | 90,960 |
| Adaptive Logic Modules (ALMs) | 45,480 (approx.) |
| LABs/CLBs | 4548 |
| Total RAM Bits | 4,520,448 bits |
| Embedded Multipliers (18x18) | 384 |
| User I/Os | 650 |
| Number of I/O Banks | 12 |
| Transceiver Channels | 12 |
| Maximum Transceiver Data Rate | 6.375 Gbps |
| PLLs (Total) | 8 (4 fast + 4 enhanced) |
| Core Voltage | 1.2 V |
| Process Technology | 90 nm CMOS |
| Package | 1508-ball FC-FBGA (FCBGA), 40 x 40 mm, 1.0 mm pitch |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +85C (Commercial) |
| Speed Grade | C3 |
| Lead Free | Yes |
| RoHS Status | Compliant |
EP2SGX90FF1508C3N Pin Configuration
| Pin A1 | I/O β General-purpose user I/O (bank 1) - see datasheet for specific assignment |
| Pin A2 | I/O β General-purpose user I/O (bank 1) |
| Pin A30 | GND β Ground |
| Pin B1 | I/O β General-purpose user I/O (bank 1) |
| Pin AF1 | I/O β General-purpose user I/O (bank 12) |
| Pin AF30 | VCC β Core/IO supply voltage (1.2V core, 3.3V I/O bank - verify per bank) |
Typical Applications
EP2SGX90FF1508C3N is suitable for 6 applications: PCIe Gen1/Gen2 Endpoint Card, XAUI / 10 Gigabit Ethernet Bridge, Serial RapidIO Backplane Aggregation, Wireless Baseband DSP Co-Processor, High-Speed Test & Measurement Equipment, ASIC Prototyping Platform.
PCIe Gen1/Gen2 Endpoint Card
The EP2SGX90FF1508C3N is well suited as the central FPGA on a PCIe add-in card targeting Gen1 (2.5 Gbps) or Gen2 (5.0 Gbps) operation. Its 12 embedded transceivers include hard PCIe PCS IP (PIPE-compliant), allowing the device to implement a complete x4 or x8 endpoint with minimal soft-logic overhead. The 90,960 logic elements and 384 (18x18) multipliers provide headroom for protocol bridge logic, scatter-gather DMA engines, and on-card signal processing, while 4,520,448 bits of block RAM accommodate packet buffering and descriptor tables.
Recommended
XAUI / 10 Gigabit Ethernet Bridge
The EP2SGX90FF1508C3N's multi-gigabit transceivers support the 3.125 Gbps lane rate required for XAUI (10 Gigabit Attachment Unit Interface), enabling 4-lane XAUI aggregation to a single 10G pipe. The Stratix II GX PCS hard IP includes 8B/10B encoding, clock-data recovery, and channel-bonding logic that simplify XAUI physical layer implementation. With 90,960 LEs and 4.5 Mbit block RAM, the device can simultaneously host the MAC layer, bridging state machines, and packet buffering for a four-port GigE-to-10G aggregator or a custom Ethernet switching fabric prototype.
Recommended
Serial RapidIO Backplane Aggregation
Stratix II GX transceivers natively support Serial RapidIO (sRIO) at 1.25, 2.5, and 3.125 Gbps per lane, and the EP2SGX90FF1508C3N provides enough logic and memory to build a multi-port sRIO switch, endpoint, or fabric bridge. The 12 transceiver channels allow 4-lane sRIO links aggregated across 3 ports, or a single 8x link with spares for redundancy. With 650 user I/Os, the FPGA can also expose parallel local-bus interfaces (RapidIO parallel, GPIO) for legacy MCU/DSP companion chips in the backplane node.
Recommended
Wireless Baseband DSP Co-Processor
With 384 (18x18) dedicated hardware multipliers and 4.5 Mbit block RAM, the EP2SGX90FF1508C3N accelerates baseband DSP functions such as FFT/iFFT, channel estimation, MIMO detection, and turbo/LDPC decoding. The fabric can implement multiple parallel DSP data paths clocked at hundreds of MHz, often replacing a dedicated ASIC or DSP cluster. Its 1.2V 90nm core keeps dynamic power manageable even at full utilization, and the 12 transceivers enable CPRI/OBSAI fronthaul links to a baseband unit or remote radio head.
Recommended
High-Speed Test & Measurement Equipment
The 6.375 Gbps transceivers, deep memory, and abundant LVDS-capable user I/Os make the EP2SGX90FF1508C3N a natural fit for protocol analyzers, logic analyzer capture engines, and arbitrary waveform generator platforms. Trigger logic, real-time compression, and pattern matching can be offloaded to dedicated DSP/multiplier blocks, while the transceivers stream pre-processed data to a host processor or storage array. The 1508-ball FC-FBGA exposes the LVDS pairs needed for high-channel-count logic acquisition.
Recommended
ASIC Prototyping Platform
Designers prototyping large ASICs and SoCs frequently target Stratix II GX FPGAs because of their capacity and abundant I/O. The EP2SGX90FF1508C3N's 90K LEs and 650 user I/Os can partition a multi-million-gate ASIC across one or two devices, while 12 high-speed transceivers emulate SerDes interfaces for pre-silicon validation. The C3 speed grade eases timing closure for large, gate-limited designs, and JTAG-based configuration allows rapid design iteration using the Quartus II design suite.
Recommended
Recommended Products Summary
Engineering reference data for EP2SGX90FF1508C3N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2SGX90FF1508C3 | EP2SGX90F1508C3N | EP2SGX90F1508C3 | EP2SGX90FF1508C3ES |
|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 1508-ball FC-FBGA (FF), 40x40mm, 1.0mm pitch | 1508-ball FC-FBGA (FF) - same | 1508-ball FC-FBGA - same | 1508-ball FC-FBGA - same | 1508-ball FC-FBGA (FF) - same |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Speed Grade | C3 (Commercial) | C3 | C3 | C3 | C3 (ES) |
| Total RAM Bits | 4,520,448 | 4,520,448 | 4,520,448 | 4,520,448 | 4,520,448 |
| User I/Os | 650 | 650 | 650 | 650 | 650 |
| Transceiver Channels | 12 (up to 6.375 Gbps) | 12 (up to 6.375 Gbps) | 12 (up to 6.375 Gbps) | 12 (up to 6.375 Gbps) | 12 (up to 6.375 Gbps) |
| Packaging Medium | Tray (N suffix) | Tape & Reel | Tray | Tape & Reel | Tray (ES) |
Key Differentiators
- Tray packaging medium with the N suffix (vs EP2SGX90FF1508C3)
- C3 commercial speed grade with full 12-transceiver complement (vs EP2SGX90FF1508I4N)
- Footprint-compatible higher-density upgrade path (vs EP2SGX130GF1508C3N)
Design Notes
The 1508-ball FC-FBGA package at 1.0 mm pitch requires a 6-8 layer PCB stack-up with 0.4-0.5 mm microvias (laser-drilled) or via-in-pad technology to fan out the BGA balls. Estimated: standard FR-4 with Tg >= 150C is acceptable for commercial temperature grades; pair each ball with a controlled-impedance escape route. The 40 x 40 mm package footprint occupies roughly 1600 mm^2 of board area and must be planned alongside decoupling capacitor placement.
Stratix II GX FPGAs at 90 nm can dissipate 10-25W under full transceiver + logic utilization. Estimated: at ambient 25C with no heatsink, junction temperature may exceed 125C for sustained high-utilization workloads. Use thermal vias under the central BGA balls, a heatsink with thermal interface material, and adequate airflow (>= 200 LFM). Consult the Stratix II GX PowerPlay early-power estimator before PCB commit.
Multi-gigabit transceiver channels require 100-ohm differential routing with intra-pair skew < 1 ps and matched length within 0.127 mm per inch of trace length. Use the Stratix II GX device handbook's recommended channel breakout - AC-coupled capacitors (typically 100 nF) are required on each transmit and receive pair. Reference planes must be uninterrupted beneath the transceiver region to preserve characteristic impedance up to 6 GHz.
Estimated: full-utilization EP2SGX90FF1508C3N can draw 8-15A on the 1.2V core rail alone, plus several amps on each of the multiple auxiliary supply rails (VCCA, VCCIO_PLL, VCC_BATT, VCCPD, VCCIO per bank). Use a multi-phase synchronous buck controller for the 1.2V core, with low-ESR ceramic decoupling (>= 200 capacitors: 0.1 uF + 10 uF + 22 uF mix) distributed under and around the BGA. Strap all GND balls to a low-impedance ground plane with multiple stitching vias.
Do not mix-and-match 'FF' and 'EF' package code suffixes - both are 1508-ball FC-FBGA but have different ball assignments and mechanical outlines, and they are NOT drop-in pin-compatible. Always verify the exact package suffix (FF, EF, GF, F1508) against the device handbook before PCB layout. Additionally, the C3 speed grade is the slowest - if timing closure is difficult, choose C4 or C5 from the same family before considering a different density.
Compliance Information
RoHS compliant and lead-free per Mouser and Ampheo product listings. AEC-Q100 is not applicable for FPGAs (FPGAs are typically not AEC-Q100 qualified as a primary qualification). REACH and halogen-free status should be verified with Intel Product Compliance for the latest declaration.
