EP910LI44-35 - 24-Macrocell Classic EPLD, 35ns, PLCC-44 | Intel / Altera
MPN: EP910LI44-35 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EP910LI44-35 Overview
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the integration density of a PLD with the erasability of UV-erasable EPROM technology. Classic EPLDs sit within the broader programmable logic hierarchy: PAL < EPLD < CPLD < FPGA. They are typically deployed as glue logic, state-machine controllers, and bus-interface bridges where deterministic timing, low standby power, and instant-on (zero-configuration) behavior are required - qualities that modern SRAM-based FPGAs cannot match without an external boot PROM.
Key features of the EP910LI44-35 include 24 macrocells organized in a PAL-type logic array, 10 dedicated input pins, 24 I/O pins, a tPD of 35 ns, a maximum internal counter frequency of 37 MHz, and CMOS-level I/O. The device supports in-system programmability via the Altera programming algorithm and is offered in both commercial and industrial temperature grades. The PLCC-44 (J-lead) package provides reliable through-hole soldering for legacy and industrial designs.
Architecturally, the EP910 uses Altera's Classic macrocell with a product-term array feeding an OR gate, a programmable register, and a tri-state output buffer. Each macrocell supports D, T, JK, or SR flip-flop modes. The I/O architecture supports true bidirectional and registered I/O, and the device includes global clock networks routed through dedicated pins for low-skew distribution. Power consumption is typically below 200 mW at full operation, with CMOS standby currents in the microamp range when the device is not switching.
Typical applications for the EP910LI44-35 include legacy industrial control, military/aerospace systems with long lifecycle requirements, telecom infrastructure glue logic, address decoding and bus arbitration in 8086/68k-based designs, and replacement of discrete 74LS/74HC logic in cost-sensitive applications. The 35 ns speed grade is well-matched to microcontrollers and microprocessors of the 1980s-1990s generation.
When designing with this EPLD, ensure that the design fits within 24 macrocells and uses only the supported product-term count per macrocell. Use the MAX+PLUS II or Quartus legacy support tools to compile the design, and program the device using an Altera-compatible programmer. The PLCC-44 socket is recommended for prototyping.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers sustain long-lifecycle EPLD-based systems.
Drop-in alternatives for EP910LI44-35 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LI44-35 (same form factor and footprint) — differing in Propagation Delay (tPD), Family, Package, Supply Voltage (VCC), Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LC44-35
✅ Drop-In✓ In Stock
$19.95 / Unit
View Datasheet →EP910LI44
✅ Drop-In✓ In Stock
$8.2 / Unit
View Datasheet →EP910LC44-40
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EP910LC44-30T
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EP910ILC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP910LI44-35 Maximum Ratings & Electrical Characteristics
| Device Family | Altera Classic EPLD |
| Series | EP910 |
| Architecture | PAL-type macrocell (EPLD) |
| Number of Macrocells | 24 |
| Number of External Clocks | 2 |
| Maximum Clock Frequency | 37 MHz |
| Propagation Delay (tPD) | 35 ns |
| Process Technology | CMOS |
| Number of Pins | 44 |
| Package Type | PLCC-44 (J-lead) |
| Mounting Type | Surface Mount / Through-Hole Socket |
| Programmability | UV-erasable / one-time programmable |
| RoHS Status | unknown |
| Logic Family | Classic EPLD |
EP910LI44-35 Pin Configuration
| Pin 1 | I/O — Bidirectional input/output pin |
| Pin 2 | I/O — Bidirectional input/output pin |
| Pin 3 | I/O — Bidirectional input/output pin |
| Pin 4 | I/O — Bidirectional input/output pin |
| Pin 5 | I/O — Bidirectional input/output pin |
| Pin 6 | I/O — Bidirectional input/output pin |
| Pin 7 | I/O — Bidirectional input/output pin |
| Pin 8 | I/O — Bidirectional input/output pin |
| Pin 9 | I/O — Bidirectional input/output pin |
| Pin 10 | I/O — Bidirectional input/output pin |
| Pin 11 | I/O — Bidirectional input/output pin |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — Bidirectional input/output pin |
| Pin 14 | I/O — Bidirectional input/output pin |
| Pin 15 | I/O — Bidirectional input/output pin |
| Pin 16 | I/O — Bidirectional input/output pin |
| Pin 17 | I/O — Bidirectional input/output pin |
| Pin 18 | I/O — Bidirectional input/output pin |
| Pin 19 | I/O — Bidirectional input/output pin |
| Pin 20 | I/O — Bidirectional input/output pin |
| Pin 21 | I/O — Bidirectional input/output pin |
| Pin 22 | I/O — Bidirectional input/output pin |
| Pin 23 | I/O — Bidirectional input/output pin |
| Pin 24 | I/O — Bidirectional input/output pin |
| Pin 25 | INPUT — Dedicated input pin |
| Pin 26 | INPUT — Dedicated input pin |
| Pin 27 | INPUT — Dedicated input pin |
| Pin 28 | INPUT — Dedicated input pin |
| Pin 29 | INPUT — Dedicated input pin |
| Pin 30 | INPUT — Dedicated input pin |
| Pin 31 | INPUT — Dedicated input pin |
| Pin 32 | INPUT — Dedicated input pin |
| Pin 33 | CLK2 — External clock input 2 |
| Pin 34 | VCC — Power supply (5V) |
| Pin 35 | CLK1 — External clock input 1 |
| Pin 36 | INPUT — Dedicated input pin |
| Pin 37 | INPUT — Dedicated input pin |
| Pin 38 | INPUT — Dedicated input pin |
| Pin 39 | INPUT — Dedicated input pin |
| Pin 40 | INPUT — Dedicated input pin |
| Pin 41 | I/O — Bidirectional input/output pin |
| Pin 42 | I/O — Bidirectional input/output pin |
| Pin 43 | I/O — Bidirectional input/output pin |
| Pin 44 | I/O — Bidirectional input/output pin |
Typical Applications
EP910LI44-35 is suitable for 6 applications: Legacy Industrial Control Logic, Microprocessor Address Decoding, Military / Aerospace Long-Lifecycle Systems, Telecom Glue Logic and Bus Arbitration, Discrete 74-Series Logic Replacement, Automotive Body Electronics (Legacy).
Legacy Industrial Control Logic
The EP910LI44-35 suits legacy industrial control systems where 24 macrocells and 35 ns propagation delay are sufficient for glue-logic, state-machine, and bus-interface functions. Its CMOS technology and PLCC-44 package deliver low standby power (microamp range) and reliable operation in factory-floor environments. The 37 MHz maximum clock frequency matches microcontroller buses of the 1980s-1990s generation, and the NRND lifecycle status means designers should stock sufficient inventory for the system's 10-20 year service life.
Recommended
Microprocessor Address Decoding
The EP910LI44-35 is well-suited for address-decoding and chip-select generation in 8086, 68k, and early ARM-based microprocessor systems. Its 24 macrocells can implement complex AND-OR decoding logic replacing multiple 74LS138 / 74LS139 chips, and its 35 ns tPD fits within one 8 MHz 8086 bus cycle. The PLCC-44 package supports both socket mounting for development boards and direct soldering for production, and CMOS technology keeps power dissipation low in battery-backed systems.
Recommended
Military / Aerospace Long-Lifecycle Systems
The EP910LI44-35 supports military and aerospace systems with long service-life requirements (15-25 years) due to its mature CMOS technology, established Altera manufacturing process, and widespread second-source availability through brokers. Its 35 ns tPD handles slow-speed avionics buses, and its -LI industrial temperature grade covers ground-mobile and shelter environments. NRND status requires proactive lifetime-buy planning; consider the EP910DM/883B for full MIL-spec screening.
Recommended
Telecom Glue Logic and Bus Arbitration
The EP910LI44-35 implements bus arbitration, interrupt steering, and protocol-conversion glue logic in telecom infrastructure equipment that was designed around Classic EPLDs. Its 24 macrocells handle multi-master bus arbitration with deterministic 35 ns timing, and the 2 external clock inputs support synchronous handshake circuits. The CMOS process keeps standby current low for always-on telecom systems, and the PLCC-44 footprint supports field-replacement through standard IC sockets.
Recommended
Discrete 74-Series Logic Replacement
The EP910LI44-35 replaces boards of 74LS, 74HC, and 74F-series discrete logic chips with a single programmable device, reducing PCB area, power consumption, and assembly cost. Its 24 macrocells can absorb 5-15 SSI/MSI logic functions depending on register usage, and its 35 ns tPD matches 74LS-series propagation delays. The PLCC-44 package provides drop-in compatibility with multi-chip 74LS layouts that have been consolidated onto EPLDs.
Recommended
Automotive Body Electronics (Legacy)
The EP910LI44-35 serves legacy automotive body-electronics modules such as central-locking controllers, lighting sequencers, and instrument-cluster glue logic where a small programmable logic device is needed to consolidate discrete components. Its CMOS process handles under-hood temperature ranges when paired with the appropriate industrial-temp grade, and its deterministic 35 ns timing supports classic CAN-bus and LIN-bus signaling rates. NRND status means automotive OEMs should plan migration to active CPLDs.
Recommended
Recommended Products Summary
Engineering reference data for EP910LI44-35 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC44-35 | EP910LI44 | EP910LC44-40 | EP910LC44-30T | EP910ILC-25 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-44 (J-lead) | PLCC-44 (J-lead) - same | PLCC-44 (J-lead) - same | PLCC-44 (J-lead) - same | PLCC-44 (J-lead) - same | PLCC-44 (J-lead) - same |
| Number of Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 35 ns | 35 ns (same) | unsuffixed | 40 ns (+14% slower) | 30 ns (-14% faster) | 25 ns (-29% faster) |
| Maximum Clock Frequency | 37 MHz | 37 MHz | 37 MHz | 37 MHz | 37 MHz | 37 MHz |
| External Clock Inputs | 2 | 2 | 2 | 2 | 2 | 2 |
| Package Material | Plastic (one-time-programmable) | Ceramic with UV window | Plastic (one-time-programmable) | Ceramic with UV window | Ceramic with UV window | Ceramic with UV window (industrial-temp) |
| Process Technology | CMOS | CMOS | CMOS | CMOS | CMOS | CMOS |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
| Architecture | PAL-type macrocell (Classic EPLD) | PAL-type macrocell (Classic EPLD) | PAL-type macrocell (Classic EPLD) | PAL-type macrocell (Classic EPLD) | PAL-type macrocell (Classic EPLD) | PAL-type macrocell (Classic EPLD) |
Key Differentiators
- Plastic PLCC-44 form factor optimized for one-time-programmable production (vs EP910LC44-35)
- Faster 35 ns speed grade vs slower 40 ns variant (vs EP910LC44-40)
- Same 24-macrocell logic capacity as EP910 family (vs EP910LC44-30T)
Design Notes
Place the EP910LI44-35 in a PLCC-44 socket for prototype development to allow easy device removal and reprogramming. For production boards, the plastic LI package can be directly surface-mounted or wave-soldered. Estimated: standard PLCC-44 sockets have a footprint of 0.95 inch square and require through-hole pads at 1.27 mm pitch. Keep decoupling capacitors (0.1 uF ceramic) within 5 mm of the VCC pin to minimize ground bounce on the internal clock network.
Route the CLK1 and CLK2 external clock inputs as short, matched-length traces to minimize clock skew across the EPLD's internal macrocell array. The 37 MHz maximum clock frequency translates to a clock period of 27 ns, leaving only a few nanoseconds of timing margin at room temperature. Avoid routing clock signals near high-current switching nodes or I/O pins that toggle simultaneously with the clock edge to prevent ground-bounce-induced setup/hold violations.
Do not exceed the 24-macrocell capacity when synthesizing designs for the EP910LI44-35; the Altera Classic fitter will fail to map designs that overflow macrocell count. Ensure each macrocell's product-term count stays within the Classic architecture limit (typically 8 product terms per OR gate with expander borrowing). Do not apply voltages outside the 5V CMOS supply range (4.5V-5.5V), and always include a power-on reset sequence because the Classic EPLD lacks built-in reset distribution across all macrocells.
The EP910LI44-35 consumes less than 200 mW typical in CMOS operation and does not require a heatsink. Estimated: at maximum toggle frequency (37 MHz, all 24 macrocells switching, 50 pF load), total power dissipation approaches 400 mW, which is still within the plastic PLCC-44 thermal envelope (theta_JA approximately 50 C/W). For high-reliability applications, derate junction temperature by 20 C below the maximum 150 C silicon limit.
Compliance Information
EP910 family predates widespread RoHS compliance documentation. Compliance status should be verified with the specific distributor or by checking the manufacturer's product environmental compliance database. Not AEC-Q100 qualified - automotive applications should consider EP910ILC-25 industrial-temp variant or migrate to MAX 7000A AEC-Q100 qualified parts.
