EP910LI-35Y - Classic EPLD 450 Gates 24 Macrocells 35ns | Altera/Intel
MPN: EP910LI-35Y ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $43.21 | $43.21 |
| 10 | $38.5 | $385.00 |
| 100 | $31.2 | $3,120.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $22.75 | $22,750.00 |
EP910LI-35Y Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines PAL-like AND/OR arrays with reprogrammable macrocells, offering a higher gate density than bipolar PALs while retaining non-volatile configuration. EPLDs belong to the broader hierarchy: programmable logic device (PLD) -> EPLD -> CMOS PLD -> Erasable PLD, sitting between simple PAL/GAL devices and modern CPLDs/FPGAs. Unlike SRAM-based FPGAs, Classic EPLDs retain their configuration in non-volatile memory and power up instantly to a known state, which simplifies system design in industrial controllers.
Key features of the EP910LI-35Y include 24 macrocells (each with a flip-flop and I/O pin), 36 dedicated inputs, an internal feedback path that allows buried macrocell registers, and a programmable clock network. The device supports multiple I/O standards on its 24 I/O pins and includes a global clock input. The 44-pin PLCC (J-lead) package provides socket-friendly field upgrades, while the "I" industrial temperature grade covers -40 °C to +85 °C operation. The "Y" lead-free finish makes the part suitable for modern RoHS-compliant assemblies, although the underlying EP910 die is a mature 1980s-1990s architecture.
Typical applications include 5 V glue logic replacement (decoders, multiplexers, comparators), address decoding in legacy microprocessor and microcontroller systems, industrial PLC interface logic, state-machine replacement in motor-control and instrumentation, and pin-compatible modernization of EP910-based designs where 35 ns timing is acceptable. The low-power "L" process makes the part attractive for power-sensitive systems that do not require higher speed grades (e.g., EP910LC-25 or EP910DC-25).
When designing with the EP910LI-35Y, ensure that all inputs are properly terminated to avoid floating CMOS inputs and that the 5 V supply is well-decoupled with 0.1 µF ceramic capacitors close to VCC pins. Because the device is one of the older Classic EPLDs, programming is performed via legacy Altera programming hardware (e.g., the Altera Logic Programmer or compatible third-party tools) and the AHDL/ABEL hardware description languages that were current at the time of introduction.
This page synthesizes distributor pricing, drop-in same-package alternatives from the EP910/EP610 family, and practical design notes not found in the original Altera datasheet.
Drop-in alternatives for EP910LI-35Y — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LI-35Y (same form factor and footprint) — differing in Package, Family, Mounting Type, Operating Temperature, Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LI-35
✅ Drop-In✓ In Stock
$25.8 / Unit
View Datasheet →EP910LI-35T
✅ Drop-In✓ In Stock
$28.5 / Unit
View Datasheet →EP910LI-40
✅ Drop-In✓ In Stock
$12.9 / Unit
View Datasheet →EP910LC-35
✅ Drop-In✓ In Stock
$18.75 / Unit
View Datasheet →EP910LC-30
✅ Drop-In✓ In Stock
$22.5 / Unit
View Datasheet →EP910DC-30
✅ Drop-In✓ In Stock
$15.6 / Unit
View Datasheet →EP910LI-35Y Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Usable Gates | 450 |
| Macrocells | 24 |
| Propagation Delay (tpd) | 35 ns |
| Supply Voltage (VCC) | 5 V |
| Process Option | L (low-power CMOS) |
| Temperature Grade | Industrial (-40 °C to +85 °C) |
| Package | PLCC-44 (J-lead) |
| Mounting Type | Surface Mount |
| Lead Finish | Lead-free (Y suffix, RoHS-compliant) |
| I/O Pins | 24 |
| Dedicated Inputs | 36 |
| Technology | CMOS EPROM/UV-erasable |
| RoHS Status | Compliant (Y suffix) |
EP910LI-35Y Pin Configuration
| Pin 1 | I/O — Input/Output macrocell pin |
| Pin 2 | I/O — Input/Output macrocell pin |
| Pin 3 | I/O — Input/Output macrocell pin |
| Pin 4 | I/O — Input/Output macrocell pin |
| Pin 5 | I/O — Input/Output macrocell pin |
| Pin 6 | I/O — Input/Output macrocell pin |
| Pin 7 | I/O — Input/Output macrocell pin |
| Pin 8 | I/O — Input/Output macrocell pin |
| Pin 9 | I/O — Input/Output macrocell pin |
| Pin 10 | I/O — Input/Output macrocell pin |
| Pin 11 | I/O — Input/Output macrocell pin |
| Pin 12 | I/O — Input/Output macrocell pin |
| Pin 13 | GND — Ground |
| Pin 14 | I/O — Input/Output macrocell pin |
| Pin 15 | I/O — Input/Output macrocell pin |
| Pin 16 | I/O — Input/Output macrocell pin |
| Pin 17 | I/O — Input/Output macrocell pin |
| Pin 18 | I/O — Input/Output macrocell pin |
| Pin 19 | I/O — Input/Output macrocell pin |
| Pin 20 | I/O — Input/Output macrocell pin |
| Pin 21 | I/O — Input/Output macrocell pin |
| Pin 22 | I/O — Input/Output macrocell pin |
| Pin 23 | I/O — Input/Output macrocell pin |
| Pin 24 | I/O — Input/Output macrocell pin |
| Pin 25 | I/O — Input/Output macrocell pin |
| Pin 26 | VCC — 5V supply voltage |
| Pin 27 | INPUT — Dedicated input pin |
| Pin 28 | INPUT — Dedicated input pin |
| Pin 29 | INPUT — Dedicated input pin |
| Pin 30 | INPUT — Dedicated input pin |
| Pin 31 | INPUT — Dedicated input pin |
| Pin 32 | INPUT — Dedicated input pin |
| Pin 33 | INPUT — Dedicated input pin |
| Pin 34 | INPUT — Dedicated input pin |
| Pin 35 | INPUT — Dedicated input pin |
| Pin 36 | INPUT — Dedicated input pin |
| Pin 37 | INPUT — Dedicated input pin |
| Pin 38 | INPUT — Dedicated input pin |
| Pin 39 | INPUT — Dedicated input pin |
| Pin 40 | INPUT — Dedicated input pin |
| Pin 41 | INPUT — Dedicated input pin |
| Pin 42 | INPUT — Dedicated input pin |
| Pin 43 | INPUT — Dedicated input pin |
| Pin 44 | INPUT — Dedicated input pin |
Typical Applications
EP910LI-35Y is suitable for 6 applications: 5V Glue Logic Replacement, Address Decoding in Microprocessor Systems, Industrial PLC Interface Logic, State Machine Replacement, Legacy System Modernization, Custom Peripheral and Bus Interface.
5V Glue Logic Replacement
The EP910LI-35Y replaces discrete 74LS/74HC glue-logic gates in 5V systems, integrating decoders, multiplexers, comparators, and parity generators into a single 24-macrocell EPLD. Its 35 ns tpd is adequate for address bus decoding, chip-select generation, and interrupt prioritization in legacy 8-bit and 16-bit microcontroller boards where 20-30 MHz clock rates dominate. The 5V single-supply operation matches classic TTL logic rails without level shifting, while the low-power L process option reduces quiescent current compared to standard-process EP910 variants, beneficial for battery-backed industrial controllers.
Recommended
Address Decoding in Microprocessor Systems
Engineers deploy the EP910LI-35Y to decode microprocessor address buses into chip-select signals for memory and peripheral ICs, replacing multiple 74LS138/74LS139 decoder packages with a single PLCC-44 device. The 24 macrocells comfortably handle full 16-bit or 20-bit address decoding with multiple output enables and bank selects, while 35 ns propagation is well within timing margins for systems running at 10-25 MHz (e.g., 8086, 68000, Z80). The non-volatile EPROM configuration ensures correct decoding at power-on without bootloader delay, which is critical for embedded controllers and industrial PLC front-ends.
Recommended
Industrial PLC Interface Logic
The EP910LI-35Y's industrial -40 °C to +85 °C operating range and 5 V tolerance make it a long-lifecycle fit for PLC interface boards, sensor-signal conditioning front-ends, and motor-control peripherals. The 36 dedicated inputs handle parallel sensor arrays, while the 24 I/O pins drive relays, optocouplers, and indicator LEDs. Engineers value the mature Altera Classic architecture for its 30+ year field-proven reliability, deterministic 35 ns tpd (no SRAM-config delay), and immunity to configuration corruption in high-EMI industrial environments. The lead-free Y finish supports modern RoHS-compliant factory automation equipment.
Recommended
State Machine Replacement
Designers consolidate discrete flip-flop state machines into a single EP910LI-35Y, encoding Mealy or Moore machines of up to 16 states across the 24 macrocell flip-flops. The 35 ns clock-to-output delay supports state-machine clock rates up to approximately 10-15 MHz with comfortable margin, making the part suitable for protocol converters, sequencers, and custom serial interfaces. The buried-register feedback feature allows internal state bits without consuming I/O pins, while programmable output polarity eliminates external inverter gates and simplifies PCB routing in legacy instrumentation designs.
Recommended
Legacy System Modernization
Engineers maintaining or replicating vintage Altera Classic EP910-based designs (1980s-1990s computer, telecom, and industrial equipment) source the EP910LI-35Y as a pin-compatible refresh part. Because the underlying architecture and PLCC-44 pinout are unchanged across speed grades, the EP910LI-35Y drops into the original socket or PCB footprint while providing the modern lead-free RoHS-compliant Y finish required by current environmental regulations. Rochester Electronics maintains licensed production for these legacy Altera parts, ensuring multi-decade supply for aviation, defense, and industrial-control customers with long equipment lifecycles.
Recommended
Custom Peripheral and Bus Interface
The EP910LI-35Y implements custom ISA, PC/104, STD, or VME bus peripherals where a CPLD is needed to bridge a microprocessor to application-specific I/O. With 24 I/O pins and 36 dedicated inputs, the device can handle bidirectional 8-bit or 16-bit bus buffering, address decoding, and interrupt handshaking in a single package. The 5V tolerance matches classic bus standards directly, and the 35 ns tpd easily satisfies bus access timing for 8 MHz ISA or 16 MHz PC/104 systems. Programmable output enables allow bus arbitration logic to be embedded alongside peripheral decoders.
Recommended
Recommended Products Summary
Engineering reference data for EP910LI-35Y — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LI-35 | EP910LI-35T | EP910LI-40 | EP910LC-35 | EP910LC-30 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel/Altera | Intel/Altera | Intel/Altera | Intel/Altera | Intel/Altera |
| Package | PLCC-44 | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tpd) | 35 ns | 35 ns | 35 ns | 40 ns | 35 ns | 30 ns |
| Temperature Grade | Industrial (-40 to +85 °C) | Industrial (-40 to +85 °C) | Industrial (-40 to +85 °C) | Industrial (-40 to +85 °C) | Commercial (0 to +70 °C) | Commercial (0 to +70 °C) |
| Process Option | L (low-power CMOS) | L (low-power CMOS) | L (low-power CMOS) | L (low-power CMOS) | L (low-power CMOS) | L (low-power CMOS) |
| Lead Finish | Lead-free (Y, RoHS) | SnPb (non-Y) | Lead-free | SnPb (non-Y) | SnPb (non-Y) | SnPb (non-Y) |
| Approx. Unit Price (qty 1) | $43.21 | $35-40 | $35-40 | $30-35 | $30-35 | $30-35 |
Key Differentiators
- Lead-free Y finish within the EP910 family (vs EP910LI-35 (non-Y, SnPb))
- Industrial temperature grade (-40 to +85 °C) (vs EP910LC-35 (commercial 0 to +70 °C))
- Low-power L process option (vs EP910DC-30 (standard power process))
Design Notes
The EP910LI-35Y operates from a single 5 V ±5% supply. Place a 0.1 µF ceramic decoupling capacitor as close as possible to each VCC pin (pin 26) and a bulk 10 µF tantalum or aluminum electrolytic capacitor on the supply rail. The low-power L process option keeps quiescent current low at idle, but dynamic supply current scales with clock frequency and output toggle rate. Estimate: a 24-macrocell design toggling at 1 MHz typically draws 20-40 mA. Ensure the 5 V regulator can supply peak transient current without sagging, which would slow the internal CMOS logic and degrade tpd.
Do not leave unused CMOS input pins floating; tie each unused dedicated input (pins 27-44) directly to GND or VCC through a 10 kΩ resistor to prevent shoot-through current and oscillation. Floating inputs on Classic EPLDs can draw milliamps per pin and may cause functional errors during configuration verification. The device is erased via UV exposure through the quartz window (older ceramic-windowed variants) - the EP910LI-35Y plastic PLCC package is one-time-programmable (OTP) in production, so design verification must be completed before committing the final JEDEC fuse map.
Although the EP910LI-35Y is a low-power CMOS EPLD, industrial-grade operation up to +85 °C ambient requires thermal management of the PLCC-44 package. Estimated: at 50 mA VCC current and 5 V supply, power dissipation is approximately 250 mW, well within the package's thermal envelope (θJA around 50 °C/W for PLCC-44 on a 4-layer board). However, in enclosed industrial enclosures with no airflow, derate ambient temperature to 70 °C maximum or provide conductive cooling. The lead-free Y solder finish has a higher reflow temperature (peak 260 °C) than SnPb, so confirm PCB assembly process compatibility.
The EP910LI-35Y's 35 ns tpd is adequate for clock rates up to approximately 10-15 MHz when accounting for setup/hold and output buffer delay. For address bus decoding, sum the EPLD tpd (35 ns) plus any external buffer delay (e.g., 74LS245 ≈ 12 ns) and compare to the CPU's memory access time. At 25 MHz 8086-style buses (40 ns cycle), the EP910LI-35Y leaves only 5 ns margin; consider EP910LC-25 or EP910DC-25 (25 ns tpd) instead. Source-synchronous outputs should be registered using the macrocell flip-flops to avoid combinational-path glitches.
Compliance Information
Y suffix denotes lead-free RoHS-compliant finish per Altera/Intel product naming convention. Halogen-free status not explicitly stated in verified data; AEC-Q100 automotive qualification not applicable for legacy Classic EPLD family.
