EP20K600CF672-2X - APEX 20KC FPGA 600K Gates 672-BGA | Altera
MPN: EP20K600CF672-2X ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $245 | $2,450.00 |
| 100 | $198 | $19,800.00 |
| 500 | $162 | $81,000.00 |
| 1,000 | $138 | $138,000.00 |
EP20K600CF672-2X Overview
An FPGA (Field Programmable Gate Array) is a programmable logic device whose function is defined by a user-supplied configuration bitstream rather than fixed mask routing. APEX 20KC sits in the broader taxonomy of programmable logic: FPGA -> programmable logic device (PLD) -> logic semiconductor -> integrated circuit. The "20KC" suffix denotes the enhanced-memory variant of the APEX 20K architecture, quadrupling embedded memory versus the original APEX 20K family and adding support for LVDS I/O, which made the family popular in telecommunications backplanes and high-throughput data-path designs of its era.
Key features include a high LUT count supporting up to 24,320 logic elements, multiple embedded system blocks providing up to 311,296 bits of RAM, support for LVDS, LVTTL, PCI, GTL+, SSTL, and other I/O standards, and a -2 speed grade offering a balance of performance and power for industrial and networking applications. The 672-ball FineLine BGA package supports high I/O count with controlled-impedance signal integrity. The device is supported by the legacy Altera Quartus II design toolchain and is widely used in long-life-cycle telecom, military, and industrial programs.
The APEX 20KC architecture uses a MultiCore fabric of LUT-based logic elements surrounded by ESBs that can each implement RAM, ROM, or content-addressable memory. The four-row I/O ring supports simultaneous operation of multiple I/O voltages and standards, enabling direct interfacing with microprocessors, memory buses, and backplane transceivers. The combination of high logic density, abundant block RAM, and LVDS capability positioned the EP20K600CF672-2X as a leading ASIC-replacement candidate in 2000s-era telecom, imaging, and DSP applications.
Typical applications include telecom backplane interface cards, ATM/SONET framing devices, high-speed DSP datapaths, military signal processing, and PCI-bus bridging ASIC replacement. The large user-I/O count also makes the device suitable for high-channel-count instrumentation and parallel data-acquisition front-ends.
When designing with this FPGA, ensure your Quartus II toolchain version supports APEX 20KC (typically Quartus II 9.1 or earlier). Decoupling follows the FineLine BGA recommended layout with at least 12 low-ESL capacitors under the package. Always verify the I/O standard assignments against the latest datasheet pin tables because pinout revisions may exist between mask sets.
This page synthesizes distributor pricing, drop-in alternatives within the APEX 20KC family, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EP20K600CF672-2X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600CF672-2X (same form factor and footprint) — differing in Process Technology, Speed Grade, Package, RoHS Status, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600CF672-2
✅ Drop-In✓ In Stock
$680 / Unit
View Datasheet →EP20K600CF672-1X
✅ Drop-In✓ In Stock
$95 / Unit
View Datasheet →EP20K600CF672
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EP20K600EFC672-2X
✅ Drop-In✓ In Stock
$115 / Unit
View Datasheet →EP20K600CF672C7
✅ Drop-In✓ In Stock
$2267.89 / Unit
View Datasheet →EP20K600CF672-2X Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Maximum Logic Elements | 24,320 |
| Typical Gates | 600,000 |
| Maximum User I/O Pins | 508 |
| Maximum Embedded RAM | 311,296 bits |
| Speed Grade | -2 |
| Package | 672-ball FineLine BGA (CF672) |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, LVDS |
| Configuration Mode | EPC (Enhanced Configuration) devices |
| Process Technology | 0.18 um CMOS |
| Mounting Type | Surface Mount (BGA) |
EP20K600CF672-2X 672-ball fineline bga (cf672) Pin Configuration Guide
Pin configuration for EP20K600CF672-2X (672-ball fineline bga (cf672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K600CF672-2X.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K600CF672-2X is suitable for 6 applications: Telecom Backplane Interface Card, ATM/SONET Framer ASIC Replacement, High-Speed DSP Datapath, Military Signal Processing, PCI Bus Bridging and ASIC Replacement, High-Channel-Count Instrumentation.
Telecom Backplane Interface Card
The EP20K600CF672-2X's 600,000 typical gates and 508 user I/O pins make it ideal for telecom backplane interface cards that aggregate multiple serial links and protocol converters. Its LVDS I/O support enables direct connection to LVDS backplane transceivers without external buffers, while the abundant block RAM (311,296 bits) implements packet buffers and lookup tables needed in framing and switching applications. Placed on a line card alongside PHY devices, the FPGA absorbs protocol conversion (e.g., SPI to UTOPIA), clock domain crossing, and link-layer processing that would otherwise require multiple ASICs.
Recommended
ATM/SONET Framer ASIC Replacement
The EP20K600CF672-2X was widely deployed as an ASIC replacement in ATM/SONET framer designs, where its 24,320 logic elements and embedded system blocks implement cell/payload assembly, scrambling, HEC generation, and pointer adjustment. The APEX 20KC architecture's combination of LUT logic and block RAM suits the mixed datapath-plus-control nature of framer designs. The -2X speed grade meets typical STM-1/OC-3 timing margins at 155 Mbps while maintaining reasonable power consumption in central-office equipment.
Recommended
High-Speed DSP Datapath
The EP20K600CF672-2X's high LUT count and 311 Kbit embedded RAM make it suitable for high-speed DSP datapaths such as FIR/FFT processing, encryption engines, and image preprocessing. The APEX 20KC ESBs implement shift-register and dual-port RAM patterns that accelerate multiply-accumulate structures common in DSP designs. The 508 user I/O pins stream parallel data to and from external ADCs/DACs, while LVDS support enables direct interface to high-speed serial converters in radar and software-defined radio applications.
Recommended
Military Signal Processing
The EP20K600CF672-2X is qualified for military temperature ranges and supports long-life-cycle programs in radar, electronic warfare, and secure communications. Its radiation tolerance and ruggedized BGA package suit avionics and naval applications where modern FPGAs may not be available. The APEX 20KC family has extensive flight heritage in defense platforms, and the 600K-gate density handles single-chip implementations of channelizers, beamformers, and signal-conditioning pipelines that previously required multiple FPGAs.
Recommended
PCI Bus Bridging and ASIC Replacement
The EP20K600CF672-2X supports PCI and PCI-X I/O standards directly, enabling PCI bus bridges and ASIC replacements that interface legacy peripheral devices to modern processors. Its 508 user I/O pins accommodate multiple PCI segments, local bus interfaces, and DMA channels in a single device. The APEX 20KC's ESBs implement scatter-gather DMA descriptors and FIFO buffers, eliminating external memory components. Designers use the FPGA to consolidate glue logic, bus bridges, and custom peripherals into one programmable device, simplifying board layout and reducing BOM.
Recommended
High-Channel-Count Instrumentation
The EP20K600CF672-2X's 508 user I/O pins enable high-channel-count instrumentation systems such as multi-channel oscilloscopes, data loggers, and parallel ATE pin electronics. Each FPGA can aggregate dozens of analog input channels, perform on-chip decimation, and stream processed data over LVDS to a host processor. The 311 Kbit block RAM implements sample buffers and trigger logic, while the LUT-based logic implements channel calibration and time-interpolation counters. The -2X speed grade supports real-time processing at hundreds of MSPS per channel.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600CF672-2X — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600CF672-2 | EP20K600CF672-1X | EP20K600CF672 | EP20K600EFC672-2X | EP20K600CF672C7 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 672-ball FineLine BGA (CF672) | 672-ball FineLine BGA (CF672) - same | 672-ball FineLine BGA (CF672) - same | 672-ball FineLine BGA (CF672) - same | 672-ball BGA - same footprint | 672-BBGA FCBGA - same |
| Family | APEX 20KC | APEX 20KC | APEX 20KC | APEX 20KC | APEX 20KC | APEX-20KC |
| Typical Gates | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 |
| Logic Elements | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 |
| Embedded RAM | 311,296 bits | 311,296 bits | 311,296 bits | 311,296 bits | 311,296 bits | 311,296 bits |
| Speed Grade | -2X | -2 | -1X | unsuffixed (standard) | -2X | C7 (commercial) |
| User I/O Pins | 508 | 508 | 508 | 508 | 508 | 508 |
Key Differentiators
- Highest-density APEX 20KC member with -2X speed grade (vs EP20K600CF672-2)
- Same silicon and package as the base EP20K600CF672 (vs EP20K600CF672 (unsuffixed))
- Industrial/extended temperature capability (vs EP20K600CF672C7)
Design Notes
The 672-ball FineLine BGA package has a typical theta_JA of approximately 15-20 C/W with a properly designed 12-layer PCB and thermal via array under the package. At typical APEX 20KC core currents, junction temperature rise is manageable but designers should follow the Altera reference PCB layout guidelines for BGA thermal management. In enclosed chassis without airflow, derate clock frequency or add a heatsink.
Use a minimum 12-layer PCB stackup with dedicated ground and power planes for the APEX 20KC BGA. Place at least 12 low-ESL 0.1uF ceramic decoupling capacitors directly under the package BGA footprint, distributed evenly across the power ball clusters. Route LVDS pairs with 100 ohm differential impedance and length-match within 50 mils. Follow the Altera APEX 20KC reference design BGA breakout for signal layers and via-in-pad where required for high-density fanout.
Do not assume Quartus II toolchain versions above 9.1 will support APEX 20KC - newer Quartus releases dropped support for legacy families. Always pin your Quartus II version to a release that supports APEX 20KC when maintaining existing bitstreams. Also verify pinout against the specific package code CF672 - some APEX 20K device variants use similar but pin-incompatible BGA codes such as CB652 or BC652 that cannot be substituted without PCB rework.
LVDS signal integrity on the 672-ball BGA requires controlled-impedance routing with reference planes on adjacent layers. Use 2D field-solver simulation for critical LVDS pairs longer than 2 inches. The APEX 20KC LVDS I/O supports up to 624 Mbps per channel but pre-emphasis and termination must be configured in the Quartus II assignment editor. Add 100 ohm differential termination at the receiver end per LVDS specification.
Compliance Information
APEX 20KC family legacy product, lifecycle obsolete. Compliance certifications not surfaced in current distributor data. Originally launched in 2000-2001 era when RoHS transition was underway - many APEX 20KC parts shipped with both RoHS and non-RoHS variants. Verify specific lot compliance with distributor before procurement.
