EP20K600CF672-3X - 600K Gate APEX 20KC FPGA, F672, -3X Speed | Intel / Altera
MPN: EP20K600CF672-3X ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $140 | $14,000.00 |
| 500 | $118 | $59,000.00 |
| 1,000 | $98 | $98,000.00 |
EP20K600CF672-3X Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), embedded memory blocks, and programmable interconnect, all controlled by SRAM-based configuration cells. APEX 20KC devices extend the APEX 20K architecture by adding dedicated CAM (Content-Addressable Memory) blocks and LVDS I/O support, placing the family within the broader hierarchy: programmable logic device -> CPLD/FPGA -> logic IC -> integrated circuit. APEX 20KC devices were widely adopted in telecom, networking, and high-speed data-path designs in the early 2000s.
Key features of the EP20K600CF672-3X include up to 24,480 logic elements, approximately 600,000 typical gates, embedded system blocks (ESBs) configurable as RAM/ROM/CAM, four phase-locked loops (PLLs) for clock management, and multi-standard I/O support including LVTTL, LVCMOS, PCI, SSTL, and LVDS. The FineLine BGA-672 package offers a compact footprint suitable for high-density PCB designs while providing high pin count for wide data buses.
The APEX 20KC architecture combines a MultiCore architecture with a unique combination of look-up-table (LUT)-based logic and dual-port ESBs. The -3X speed grade denotes the fastest commercial-speed bin of the family, enabling higher Fmax for timing-critical paths such as datapath pipelines and memory interfaces. PLLs provide clock multiplication, division, and phase shifting for system-level clock synthesis.
Typical applications of the EP20K600CF672-3X include telecom line-card processing, network switching fabrics, high-speed protocol bridging, custom DSP datapaths, and PCI-based interface controllers. Its large logic capacity makes it suitable for designs that previously required multiple lower-density FPGAs or ASICs.
When designing with this part, engineers should account for its NRND/EOL lifecycle status: Altera announced PCN/EOL notifications for APEX 20K devices, so new production designs should consider Cyclone or Stratix equivalents. Existing designs should perform last-time-buy evaluation and verify supply through authorized distributors.
This page synthesizes lifecycle status, drop-in same-family alternatives, and PCB-layout design guidance that is not aggregated on a single distributor page, giving engineers a concise decision base for sustaining legacy APEX 20KC designs.
Drop-in alternatives for EP20K600CF672-3X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600CF672-3X (same form factor and footprint) — differing in Process Technology, Speed Grade, Package, RoHS Status, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600CF672-3
✅ Drop-In✓ In Stock
$99.5 / Unit
View Datasheet →EP20K600CF672-2X
✅ Drop-In✓ In Stock
$138 / Unit
View Datasheet →EP20K600CF672-2
✅ Drop-In✓ In Stock
$680 / Unit
View Datasheet →EP20K600CF672-1X
✅ Drop-In✓ In Stock
$95 / Unit
View Datasheet →EP20K600CF672
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EP20K600CB672C8
✅ Drop-In✓ In Stock
$245 / Unit
View Datasheet →EP20K600CF672-3X Maximum Ratings & Electrical Characteristics
| Series | APEX 20KC |
| Family | APEX 20K (MultiCore) |
| Typical Gates | 600,000 |
| Logic Elements | 24,480 |
| Maximum System Gates | 1,537,000 |
| Embedded System Blocks (ESBs) | 312 |
| Maximum RAM Bits | 311,296 |
| Maximum User I/O Pins | 508 |
| PLLs | 4 |
| Package | 672-pin FineLine BGA (F672) |
| Mounting Type | Surface Mount (BGA) |
| Speed Grade | -3X (fastest) |
| Operating Temperature | 0C to +85C (commercial) |
| Process Technology | 0.18 um CMOS, SRAM-based |
| Configuration Method | SRAM, serial/parallel, EPC support |
EP20K600CF672-3X 672-pin fineline bga (f672) Pin Configuration Guide
Pin configuration for EP20K600CF672-3X (672-pin fineline bga (f672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K600CF672-3X.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K600CF672-3X is suitable for 6 applications: Telecom Line-Card Processing, Network Switching Fabric Interface, High-Speed Protocol Bridging, Custom DSP Datapath Engine, PCI-Based Interface Controllers, Industrial Test and Measurement Instrumentation.
Telecom Line-Card Processing
The EP20K600CF672-3X delivers 24,480 logic elements and 508 user I/O pins, making it well suited to telecom line-card designs that integrate TDM framers, HDLC controllers, and ATM/AAL2 segmentation engines on a single device. The four on-chip PLLs enable generation of multiple clock domains (T1/E1, E3/DS3, STS-1) from a single reference oscillator, eliminating external clock-generator ICs. The 311 Kbits of embedded RAM support cell-buffer FIFOs and look-up tables for routing tables. The -3X speed grade delivers the highest Fmax in the family, critical for STS-1 / STM-0 line rates and above.
Recommended
Network Switching Fabric Interface
With 24,480 logic elements, 312 ESBs, and 508 I/O pins, the EP20K600CF672-3X can host a complete switching-fabric interface including MAC controllers, CAM lookup logic, queue managers, and PCI/UTOPIA system-side interfaces. The on-chip CAM blocks via the ESBs accelerate L2/L3 address lookups at wire speed. LVDS I/O support enables direct connection to serializer/deserializer (SERDES) chips for gigabit links. The 672-ball FineLine BGA provides the high pin count needed for 32-bit or 64-bit datapath connections to network processors.
Recommended
High-Speed Protocol Bridging
Protocol bridges such as SPI-to-PCI, UART-to-USB, or custom serial-to-parallel converters benefit from the EP20K600CF672-3X's large logic capacity and 311 Kbits of dual-port RAM, which allows buffer-based bridge designs with handshaking flow control. The -3X speed grade supports the high clock rates required for SPI peripherals running above 50 MHz and for USB 2.0 full-speed bit-stuffing logic. 508 user I/O lets the bridge expose multiple peripheral interfaces simultaneously without external mux logic.
Recommended
Custom DSP Datapath Engine
DSP datapath engines for baseband processing, image processing, or custom FIR/IIR filters can leverage the EP20K600CF672-3X's 24,480 logic elements and 311 Kbits of embedded memory to build high-throughput pipelined multipliers and accumulators. The four PLLs support multi-rate sample-clock generation for narrowband and wideband processing paths. The -3X speed grade provides the Fmax headroom needed for 16-bit x 16-bit multiply-accumulate pipelines at sample rates above 100 MHz. 508 user I/O accommodate wide parallel data buses to external ADC/DAC converters.
Recommended
PCI-Based Interface Controllers
The EP20K600CF672-3X supports the PCI 33 MHz / 66 MHz interface directly via its 5 V-tolerant I/O banks, with built-in compliance to the PCI Local Bus Specification. 24,480 logic elements easily host a PCI Target or Master controller plus DMA engine, command FIFOs, and interrupt logic. The 311 Kbits of embedded memory accommodate scatter-gather descriptor tables and DMA buffers. For multi-slot systems, the 508 user I/O support arbitration signals for multiple PCI devices. The 672-ball FineLine BGA simplifies board routing of the 32-bit PCI bus plus sideband signals.
Recommended
Industrial Test and Measurement Instrumentation
Test and measurement instruments such as logic analyzers, protocol analyzers, and ATE pin-electronics benefit from the EP20K600CF672-3X's logic capacity, on-chip memory, and -3X speed grade to handle real-time capture and triggering. The 311 Kbits of dual-port RAM function as deep trace buffers, while the 508 user I/O accept multiple channels of high-speed probes simultaneously. Four PLLs derive multiple internal sampling clocks from a single precision reference. The device's commercial temperature range (0C to 85C) and FineLine BGA package suit benchtop and rack-mount instrument designs.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600CF672-3X — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600CF672-3 | EP20K600CF672-2X | EP20K600CF672-1X | EP20K600CB672C8 |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Package | 672-ball FineLine BGA (F672) | 672-ball FineLine BGA (F672) - same | 672-ball FineLine BGA (F672) - same | 672-ball FineLine BGA (F672) - same | 672-ball BGA (B672) - same family |
| Typical Gates | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 |
| Logic Elements | 24,480 | 24,480 | 24,480 | 24,480 | 24,480 |
| Maximum User I/O | 508 | 508 | 508 | 508 | 488 |
| Speed Grade | -3X (fastest) | -3 | -2X | -1X | -8 (commercial) |
| PLLs | 4 | 4 | 4 | 4 | 4 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. Unit Price (1 qty, USD) | $185 | $175-185 | $140-160 | $110-130 | $160-180 |
Key Differentiators
- Highest-density APEX 20KC member at -3X speed grade (vs EP20K600CF672-2X)
- Drop-in compatibility with all F672 APEX 20K 600K variants (vs EP20K600CB672C8 (B672 package))
- Four on-chip PLLs for flexible clock synthesis (vs EP20K400FC672-3X)
Design Notes
The EP20K600CF672-3X uses a 1.0 mm-pitch 672-ball FineLine BGA, which requires a multi-layer PCB (typically 8+ layers) with microvia or via-in-pad technology to route signals out of the BGA array. Use the Altera-provided land-pattern and pin-out files as the authoritative source; do not synthesize footprints from package outline alone. Plan for at least one full reference plane layer beneath the BGA for clean power delivery to the core and I/O banks.
Provide separate decoupling for VCCINT (core), VCCIO (I/O banks), VCCP (PCI clamp), and PLL analog supplies (VCCA_PLL, VCCD_PLL). Place 0.1 uF X7R ceramic decoupling caps within 50 mils of every supply ball, and bulk capacitors (10-100 uF) at each power rail entry point. The four PLLs require isolated analog supplies with pi-filter (ferrite bead + caps) to prevent digital switching noise from coupling into PLL loops and causing jitter.
Because the APEX 20KC family uses SRAM-based configuration, the bitstream is volatile and must be reloaded at every power-up from a configuration device (EPC1, EPC2, EPC4, EPC8, EPC16) or a microprocessor. Do not assume the FPGA retains its configuration after a power cycle. For in-system reprogramming, route JTAG (TCK, TMS, TDI, TDO) to a test header or boundary-scan chain. Verify nCONFIG, nSTATUS, and CONF_DONE behavior during board bring-up to detect configuration failures early.
The 672-ball FineLine BGA package concentrates heat in a small area; estimate worst-case junction temperature from total power dissipation multiplied by theta_JA (approximately 8-12 C/W with proper PCB thermal design, depending on copper area and airflow). For sustained operation above 70 percent utilization, plan for a thermal copper pad under the BGA and possibly forced-air cooling to keep Tj below 100 C in commercial temperature range designs.
Compliance Information
RoHS and lead-free status depend on date code and assembly lot. Original APEX 20KC family pre-dates RoHS enforcement; later production runs and many authorized aftermarket suppliers provide RoHS-compliant parts with C-of-C documentation. AEC-Q100 not applicable to FPGAs.
