Intel

EP2AGX260FF35I3N - 244K LE Arria II GX FPGA | Intel (Altera)

Name: EP2AGX260FF35I3N - 244K LE Arria II GX FPGA | Intel (Altera)
Brand: Intel
SKU: EP2AGX260FF35I3N
Price: 1390 USD
Availability: InStock

MPN: EP2AGX260FF35I3N ⚠ Last Time Buy

In Stock Ships in 1-3 business days

1.0 V (nominal) Vdss 1152-BBGA, FCBGA (35 x 35 mm) Package 500 MHz Speed 12,038,144 Memory

From $1390 USD / Unit

MOQ: 1 |

Price updated: 2026-09-08

Volume Pricing

Qty	Unit Price	Extended
1	$1850	$1,850.00
10	$1720	$17,200.00
100	$1595	$159,500.00
500	$1480	$740,000.00
1,000	$1390	$1,390,000.00

ℹ️ All prices are in USD

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EP2AGX260FF35I3N Overview

The Intel (formerly Altera) EP2AGX260FF35I3N is a high-density Arria II GX field-programmable gate array (FPGA) integrating 244,188 logic elements, 12,038,144 bits of embedded memory, and 612 user I/Os in a 1152-ball flip-chip BGA (FCBGA, 35 x 35 mm) package. The Arria II GX family targets mid-range applications requiring integrated transceivers for high-speed serial connectivity, combining a hardened 6.375 Gbps transceiver PHY with a low-power adaptive logic module (ALM) fabric to deliver a balanced power/performance profile for protocol bridging, video processing, and DSP-intensive designs.

An FPGA (field-programmable gate array) is a reconfigurable semiconductor device whose logic functionality is defined after manufacture by the user. Architecturally the FPGA sits within the broader category of programmable logic devices (PLDs) and competes with CPLDs on the low end and ASICs on the high end. FPGAs consist of an array of configurable logic blocks (ALMs/LEs), programmable interconnect, embedded memory (block RAM), DSP blocks, clock management PLLs, and high-speed transceiver/IO tiles. They are widely used to prototype logic, accelerate parallel algorithms, and provide reconfigurable interfaces in telecom, broadcast, defense, and industrial systems.

Key features of the EP2AGX260FF35I3N include 10260 LABs/CLBs, 612 I/O pins, embedded 6.375 Gbps multi-gigabit transceivers for protocols such as PCIe Gen1/Gen2, Serial RapidIO, XAUI, CPRI, and Gbps Ethernet, hard PCIe Gen1/Gen2 IP blocks, up to 16 global clock networks, and dynamic on-chip termination (OCT). The device operates from a 1.0 V core supply, supports configuration via fast passive parallel (FPP), active serial (AS), passive serial (PS), and JTAG modes, and is rated for the industrial temperature range (-40 C to +100 C case).

The Arria II GX architecture uses an adaptive logic module (ALM) building block that combines 8-input fracturable look-up tables with dedicated arithmetic and register chains, increasing effective logic density by approximately 25 % over previous-generation 4-input LUT architectures. Multi-track routing and optimized pipeline registers enable sustained DSP throughput above 300 MHz, which is essential for wireless baseband and video codec pipelines. Hard memory controllers and variable-precision DSP blocks coexist with user-configurable fabric, allowing designers to instantiate high-bandwidth packet buffers and FFT engines without consuming programmable logic.

Typical applications include wireless baseband processing (LTE, WiMAX), video infrastructure (broadcast encoders, transcoders, display controllers), high-speed serial protocol bridging (PCIe, Serial RapidIO, Gbps Ethernet), test and measurement instrumentation, and radar signal processing. Designers typically pair the FPGA with DDR2/DDR3 SDRAM, external flash for configuration storage, and an FPGA power supply such as the Intel Enpirion EN63A0QI or Linear Technology (Analog Devices) LTM4620/LTM4644 multi-rail controller to meet the 1.0 V core and 2.5 V/3.3 V aux rail requirements.

When designing with this device, ensure 0.1 uF + 10 uF decoupling is placed adjacent to every power pin, follow the FCBGA escape and via-in-pad recommendations in the Arria II device handbook, and use Quartus II (or the later Quartus Prime) for synthesis, place-and-route, and timing closure. Estimating: total power at full transceiver utilization approaches 15-20 W and requires a multi-layer PCB with at least 2 oz copper and a thermal management plan (heat spreader or heatsink with controlled airflow) to keep the junction temperature within limits.

This page synthesizes distributor pricing, same-package drop-in alternatives drawn from the Site MPN list, and practical FPGA design notes not found in a single datasheet reference, giving design engineers a one-stop engineering summary for the EP2AGX260FF35I3N.

Drop-in alternatives for EP2AGX260FF35I3N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP2AGX260FF35I3N (same form factor and footprint) — differing in Package, Operating Temperature, Speed Grade, Process Technology, Mounting Type.

EP2AGX260FF35C4N

Altera

Package: 1152-ball FC-FBGA

Operating Temperature: Commercial (0C to +85C)

Speed Grade: -4