Intel

EP3SE260F1152I3N - 255K Logic Elements Stratix III E FPGA | Intel

MPN: EP3SE260F1152I3N ⚠ Last Time Buy

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0.9 V to 1.1 V selectable Vdss 1152-BBGA, FCBGA (FC-FBGA) Package 500 MHz Speed

From $3360 USD / Unit

MOQ: 1 |

Price updated: 2026-09-09

Volume Pricing

Qty	Unit Price	Extended
1	$4200	$4,200.00
10	$3990	$39,900.00
100	$3780	$378,000.00
250	$3520	$880,000.00
500	$3360	$1,680,000.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EP3SE260F1152I3N Overview

The Intel (Altera) EP3SE260F1152I3N is a high-density Stratix III E Field-Programmable Gate Array (FPGA) featuring 255,000 logic elements, 16,672,768 embedded memory bits, and 744 maximum user I/Os, housed in a 1152-ball FC-FBGA package. Built on a 65 nm CMOS process, the device operates at a selectable core voltage of 0.9 V to 1.1 V with a maximum internal clock frequency of approximately 500 MHz.

An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs) connected via programmable interconnect, allowing engineers to implement custom digital circuits after fabrication. FPGAs sit within the broader hierarchy of programmable logic devices (PLDs), above simple CPLDs (Complex Programmable Logic Devices) and below ASICs (Application-Specific Integrated Circuits) in terms of integration density. The Stratix III E family specifically targets high-performance DSP, memory-rich, and transceiver-equipped designs.

Key features include 10,200 Logic Array Blocks (LABs), embedded memory blocks for high-bandwidth buffering, dedicated DSP blocks for fixed- and floating-point arithmetic, and selectable core voltage support (0.9 V/1.0 V/1.1 V) for power/performance trade-off. The device supports JTAG boundary-scan configuration, supports up to 744 user I/Os, and is rated industrial-grade (I3N suffix: -40 °C to +100 °C operating).

Architecturally, the Stratix III E uses a tile-based logic structure, on-chip memory columns, and adaptive logic modules (ALMs) with 8-input fracturable look-up tables. Process technology is 65 nm CMOS, enabling high logic density at moderate static power versus 90 nm predecessors. Embedded transceivers and hard PCIe, memory controller, and DSP blocks allow designers to build high-throughput pipelines without soft IP overhead.

Typical applications include high-end digital signal processing, ASIC prototyping, high-speed data acquisition front-ends, telecom baseband processing, and military/aerospace signal processing. The wide memory bandwidth also suits image processing and software-defined radio prototyping.

When designing with this device, allocate sufficient PCB layers for power delivery and signal integrity—1152 balls require careful escape routing and a 12+ layer stack-up with buried vias. Use Intel Quartus II for synthesis, place-and-route, and timing closure; static timing analysis and signal integrity verification are mandatory at this density.

This page synthesizes distributor pricing, drop-in same-package Stratix III E alternatives, and practical design notes not found in the manufacturer datasheet, providing engineering value beyond what is currently in public distributor listings.

Drop-in alternatives for EP3SE260F1152I3N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP3SE260F1152I3N (same form factor and footprint) — differing in Package, Core Voltage, Operating Temperature, Family, Speed Grade.

EP3SE260F1152C2N

Intel

Family: FPGA - Field Programmable Gate Array