Intel

EP3SE260F1152C2N - Stratix III E FPGA, 255K LE, 1152-FCBGA | Intel

MPN: EP3SE260F1152C2N ✗ End of Life

In Stock Ships in 1-3 business days

1.1 V Vdss 1152-BBGA, FCBGA Package 600 MHz Speed 16672768 Memory

From $11000 USD / Unit

MOQ: 1 |

Price updated: 2026-09-09

Volume Pricing

Qty	Unit Price	Extended
1	$16967.12	$16,967.12
10	$15200	$152,000.00
100	$13500	$1,350,000.00
500	$12100	$6,050,000.00
1,000	$11000	$11,000,000.00

ℹ️ All prices are in USD

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EP3SE260F1152C2N Overview

The Intel EP3SE260F1152C2N is a high-density Stratix® III E Field Programmable Gate Array (FPGA) delivering 255,000 logic elements and 10,200 LABs/CLBs in a 1152-pin FCBGA package, fabricated on a 65 nm process node with 1.1 V core supply. It provides 744 maximum user I/Os and 16,672,768 bits of embedded memory, targeting high-throughput digital signal processing, telecommunications backplanes, and ASIC prototyping.

An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs/LABs), programmable interconnects, and dedicated silicon resources such as block RAM, DSP blocks, and high-speed transceivers. FPGAs occupy the programmable-logic tier of the broader integrated-circuit hierarchy: IC > digital IC > programmable logic > FPGA. Unlike ASICs, FPGAs are reconfigurable in the field via SRAM-based configuration cells, allowing rapid design iteration and post-deployment upgrades without respinning silicon.

Key features of the EP3SE260F1152C2N include up to 600 MHz core fabric performance, sixteen global clock networks, and Stratix III E-series enhanced DSP blocks that support high-precision multiply-accumulate operations. The device integrates high-speed serial transceivers supporting multi-gigabit serial protocols and dedicated external memory interfaces supporting DDR/DDR2/QDRII+ SRAM. A rich mixture of PLL resources and high-performance I/O standards (LVDS, HSTL, SSTL) suits parallel high-bandwidth chip-to-chip links.

Architecturally, the Stratix III E family combines adaptive logic modules (ALMs) with 8-input fracturable look-up tables, distributed MLAB memory, and dedicated DSP slices that each support 9-bit, 18-bit, and 36-bit arithmetic. The 65 nm process and 1.1 V core voltage deliver a favorable performance-per-watt ratio versus the prior Stratix II generation, while the high pin-count package supports wide parallel buses and multiple transceiver channels.

Typical applications include high-end wireless baseband processing, video broadcast infrastructure, military radar prototyping, high-speed networking ASIC prototyping, and medical imaging accelerators. Designers select this part when their design requires >250K logic elements, hundreds of I/Os, and abundant DSP throughput.

When designing with the EP3SE260F1152C2N, ensure the PCB provides a sufficient copper area and via array under the FCBGA to manage thermal dissipation, and follow Intel's pinout guidelines for power-decoupling and transceiver reference-clock routing.

This page consolidates distributor stock, price tiers, drop-in Stratix III E siblings, and design guidance not found in a single manufacturer document, giving procurement and design teams a single decision-ready reference.

Drop-in alternatives for EP3SE260F1152C2N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP3SE260F1152C2N (same form factor and footprint) — differing in Package, Speed Grade, Operating Temperature, Process Technology, Series.

EP3SE110F1152C2N

Altera

Package: 1152-ball FC-FBGA (35x35 mm)

Speed Grade: C2

Operating Temperature: 0 °C to +85 °C (Commercial)