Intel

EPF10K130EQC240-1N - 130K Gates FLEX 10KE FPGA, 240-PQFP | Intel

MPN: EPF10K130EQC240-1N ✗ End of Life
In Stock Ships in 1-3 business days
2.375 V to 2.625 V (2.5 V nominal) Vdss 240-BFQFP / 240-PQFP, 32 × 32 mm Package 333.33 MHz Speed 64 Kbit (4 × EAB, 2,048 bits each) Memory
From $88.4 USD / Unit
MOQ: 1 |
Price updated: 2026-09-11
Volume Pricing
Qty Unit Price Extended
1 $145 $145.00
10 $128.5 $1,285.00
100 $112 $11,200.00
250 $99.75 $24,937.50
500 $88.4 $44,200.00
ℹ️ All prices are in USD

EPF10K130EQC240-1N Overview

The Intel (formerly Altera) EPF10K130EQC240-1N is a FLEX 10KE family Field-Programmable Gate Array (FPGA) integrating 130,000 system gates with 6,656 logic elements and 65,536 bits of embedded SRAM, fabricated on a 0.22 µm (some sources cite 0.25 µm) CMOS process and housed in a 240-pin Plastic Quad Flat Pack (PQFP / 240-BFQFP) measuring 32x32 mm. The device operates from a 2.375 V to 2.625 V (2.5 V nominal) core supply, supports 186 user I/Os, and contains 832 Logic Array Blocks (LABs) implementing a built-in SRAM configuration memory so the bitstream reloads on every power-up.

A Field-Programmable Gate Array is a reconfigurable digital integrated circuit that combines programmable logic elements, an interconnect matrix, and I/O blocks in a single die. Within the broader programmable-logic taxonomy, FPGAs sit above small CPLDs and below ASICs in density; the FLEX 10KE family in particular targets glue-logic, bus-bridging, and mid-density state-machine designs of the late 1990s/early 2000s, before the Cyclone and Stratix families displaced FLEX 10KE in new designs. Engineers chose the FLEX 10KE family for SRAM-based reconfigurability, embedded memory blocks, and the mature Quartus II design-flow support.

Key specifications include 64 Kbit embedded block RAM (EAB), 342,000 maximum system gates, 4 Embedded Array Blocks (EABs) of 2,048 bits each, 333.33 MHz maximum internal operating frequency, and -40 °C to +85 °C commercial operating temperature range (note the -1N speed grade). The -1N suffix designates the faster -1 speed grade combined with an industrial/lead-free reflow profile; the package is lead-free (Pb-free) and RoHS compliant, while older -1 / -2 / -3 grades used SnPb lead finish. Compared with the -3 (slowest) grade, the -1 grade delivers the highest internal performance in this family.

Typical applications include telecom interface cards (T1/E1, Utopia, POS-PHY bridging), industrial control boards, mid-density glue logic between microprocessors and peripherals, ISA/PCI bus bridges, and legacy replacement of 74-series TTL arrays in long-lifecycle equipment. The 186 user I/Os and 64 Kbit of embedded RAM also make it suitable for protocol converters and small packet-processing engines on FPGA fabric.

When designing with this part, ensure the 2.5 V core rail is well decoupled with 0.1 µF and 10 µF capacitors near each supply pin, and route all 186 I/Os through 5 V-tolerant banks if the board mixes 3.3 V and 5 V logic. Quartus II (legacy) or the Quartus Prime FLEX 10KE device-support add-on is required for synthesis, fitting, and bitstream generation.

This page combines distributor pricing, SameFrame pin-migration alternatives, and practical design guidance not found in the original FLEX 10KE datasheet, helping engineers evaluating EOL inventory or performing legacy board-maintenance sourcing.

Drop-in alternatives for EPF10K130EQC240-1N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF10K130EQC240-1N (same form factor and footprint) — differing in Operating Temperature, Total RAM Bits, Package, Mounting Type, Configuration Method.

Intel
Operating Temperature: 0 °C to 70 °C (commercial)
Mounting Type: Surface Mount
Compare with EPF10K130EQC240-1N →
Altera
Operating Temperature: 0C to +70C (Commercial, N suffix)
Total RAM Bits: 49152
Mounting Type: Surface Mount
Compare with EPF10K130EQC240-1N →
Altera
Operating Temperature: 0 C to +70 C (Commercial)
Package: 240-pin PQFP / BFQFP (32x32 mm)
Mounting Type: Surface Mount (Gull-wing)
Compare with EPF10K130EQC240-1N →
Intel
Operating Temperature: 0 °C to +70 °C (Commercial)
Total RAM Bits: 65,536 bits
Package: 240-BQFP (PQFP), 32 x 32 mm
Compare with EPF10K130EQC240-1N →
Intel
Total RAM Bits: 6,912 bits
Package: 240-pin PQFP (RQFP-240), gull-wing, surface mount
Mounting Type: Surface Mount (Gull Wing)
Compare with EPF10K130EQC240-1N →
Altera
Operating Temperature: -40 °C to +85 °C (Industrial, I grade)
Total RAM Bits: 65,536 bits (EAB)
Package: 240-BFQFP (PQFP)
Compare with EPF10K130EQC240-1N →
Altera
Operating Temperature: 0 °C to +85 °C (Commercial)
Total RAM Bits: 40960
Package: 240-pin PQFP / BFQFP
Compare with EPF10K130EQC240-1N →

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EPF10K130EQC240-1

✅ Drop-In
Altera
📦 240-PQFP (32x32 mm)
FLEX 10KE · 130,000 · 6,656 · 4 · 65,536 · 186 · 2.5 V (2.375 V to 2.625 V)

✓ In Stock

$92.5 / Unit

View Datasheet →

EPF10K130EQC240-2N

✅ Drop-In ⚠️ 参数待验证
📦 240-PQFP (32x32 mm)
same die, same PQFP footprint, but -2 (slower) speed grade; Fmax reduced vs -1 grade

📋 Reference alternative (not in catalog)

EPF10K130EQC240-3N

✅ Drop-In
Intel
📦 240-PQFP (32x32 mm)
FLEX 10KE · FLEX-10KE® · 6,656 · 832 · 65,536 bits · 186 · 342,000 (typical 49,152) · 200 MHz

✓ In Stock

$19.8 / Unit

View Datasheet →

EPF10K100EQC240-1N

✅ Drop-In
Intel
📦 240-PQFP (32x32 mm)
FLEX 10KE · 4,992 · 100,000 · 624 · 49,152 · 189 · 333.33 MHz · 0.22 µm CMOS

✓ In Stock

$55.95 / Unit

View Datasheet →

EPF10K100EQC240-2N

✅ Drop-In
Altera
📦 240-PQFP (32x32 mm)
FLEX 10KE · 4992 · 49152 · 624 · 100000 · 189 · 2.375 V to 2.625 V (typ. 2.5 V) · 3.3 V multi-voltage I/O

✓ In Stock

$18.4 / Unit

View Datasheet →

EPF10K130EQC240-1N Maximum Ratings & Electrical Characteristics

Family FLEX 10KE
Logic Elements 6,656
System Gates (typical) 130,000
Maximum System Gates 342,000
Total RAM Bits 65,536
Embedded Memory 64 Kbit (4 × EAB, 2,048 bits each)
Logic Array Blocks (LABs) 832
User I/Os 186
Number of I/O Pins 240 (package pin count)
Supply Voltage (VCCINT) 2.375 V to 2.625 V (2.5 V nominal)
Process Technology 0.22 µm CMOS (some sources cite 0.25 µm)
Maximum Internal Frequency 333.33 MHz
Program Memory Type SRAM (volatile, reload on power-up)
Package 240-BFQFP / 240-PQFP, 32 × 32 mm
Speed Grade -1 (fastest grade for FLEX 10KE family)
Suffix Code N (lead-free / Pb-free reflow profile)
Operating Temperature 0 °C to +70 °C commercial (per -1 grade)
Mounting Type Surface Mount (gull-wing leads)
RoHS Status Compliant (Pb-free)
Part Status Obsolete (per Arrow listing)

EPF10K130EQC240-1N Pin Configuration

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Pin 1 I/O — User I/O pin (bank 1)
Pin 2 I/O — User I/O pin (bank 1)
Pin 3 I/O — User I/O pin (bank 1)
Pin 4 VCCIO1 — I/O bank 1 supply voltage
Pin 5 I/O — User I/O pin (bank 1)
Pin 6 I/O — User I/O pin (bank 1)
Pin 7 GND — Ground
Pin 8 I/O — User I/O pin (bank 1)
Pin 9 I/O — User I/O pin (bank 1)
Pin 10 I/O — User I/O pin (bank 1)
Pin 11 I/O — User I/O pin (bank 1)
Pin 12 I/O — User I/O pin (bank 1)
Pin 13 I/O — User I/O pin (bank 1)
Pin 14 I/O — User I/O pin (bank 1)
Pin 15 VCCINT — Core supply voltage (2.5 V nominal)
Pin 16 VCCINT — Core supply voltage (2.5 V nominal)
Pin 17 GND — Ground
Pin 18 I/O — User I/O pin (bank 2)
Pin 19 I/O — User I/O pin (bank 2)
Pin 20 I/O — User I/O pin (bank 2)
Pin 21 I/O — User I/O pin (bank 2)
Pin 22 I/O — User I/O pin (bank 2)
Pin 23 I/O — User I/O pin (bank 2)
Pin 24 VCCIO2 — I/O bank 2 supply voltage
Pin 25 I/O — User I/O pin (bank 2)
Pin 26 I/O — User I/O pin (bank 2)
Pin 27 GND — Ground
Pin 28 I/O — User I/O pin (bank 2)
Pin 29 I/O — User I/O pin (bank 2)
Pin 30 I/O — User I/O pin (bank 2)
Pin 31 I/O — User I/O pin (bank 2)
Pin 32 I/O — User I/O pin (bank 2)
Pin 33 I/O — User I/O pin (bank 2)
Pin 34 I/O — User I/O pin (bank 2)
Pin 35 VCCINT — Core supply voltage (2.5 V nominal)
Pin 36 VCCINT — Core supply voltage (2.5 V nominal)
Pin 37 GND — Ground
Pin 38 I/O — User I/O pin (bank 3)
Pin 39 I/O — User I/O pin (bank 3)
Pin 40 I/O — User I/O pin (bank 3)
Pin 41 I/O — User I/O pin (bank 3)
Pin 42 I/O — User I/O pin (bank 3)
Pin 43 I/O — User I/O pin (bank 3)
Pin 44 VCCIO3 — I/O bank 3 supply voltage
Pin 45 I/O — User I/O pin (bank 3)
Pin 46 I/O — User I/O pin (bank 3)
Pin 47 GND — Ground
Pin 48 I/O — User I/O pin (bank 3)
Pin 49 I/O — User I/O pin (bank 3)
Pin 50 I/O — User I/O pin (bank 3)
Pin 51 I/O — User I/O pin (bank 3)
Pin 52 I/O — User I/O pin (bank 3)
Pin 53 I/O — User I/O pin (bank 3)
Pin 54 I/O — User I/O pin (bank 3)
Pin 55 VCCINT — Core supply voltage (2.5 V nominal)
Pin 56 VCCINT — Core supply voltage (2.5 V nominal)
Pin 57 GND — Ground
Pin 58 I/O — User I/O pin (bank 4)
Pin 59 I/O — User I/O pin (bank 4)
Pin 60 I/O — User I/O pin (bank 4)
Pin 61 I/O — User I/O pin (bank 4)
Pin 62 I/O — User I/O pin (bank 4)
Pin 63 I/O — User I/O pin (bank 4)
Pin 64 VCCIO4 — I/O bank 4 supply voltage
Pin 65 I/O — User I/O pin (bank 4)
Pin 66 I/O — User I/O pin (bank 4)
Pin 67 GND — Ground
Pin 68 I/O — User I/O pin (bank 4)
Pin 69 I/O — User I/O pin (bank 4)
Pin 70 I/O — User I/O pin (bank 4)
Pin 71 I/O — User I/O pin (bank 4)
Pin 72 I/O — User I/O pin (bank 4)
Pin 73 I/O — User I/O pin (bank 4)
Pin 74 I/O — User I/O pin (bank 4)
Pin 75 VCCINT — Core supply voltage (2.5 V nominal)
Pin 76 VCCINT — Core supply voltage (2.5 V nominal)
Pin 77 GND — Ground
Pin 78 I/O — User I/O pin (bank 5)
Pin 79 I/O — User I/O pin (bank 5)
Pin 80 I/O — User I/O pin (bank 5)
Pin 81 I/O — User I/O pin (bank 5)
Pin 82 I/O — User I/O pin (bank 5)
Pin 83 I/O — User I/O pin (bank 5)
Pin 84 VCCIO5 — I/O bank 5 supply voltage
Pin 85 I/O — User I/O pin (bank 5)
Pin 86 I/O — User I/O pin (bank 5)
Pin 87 GND — Ground
Pin 88 I/O — User I/O pin (bank 5)
Pin 89 I/O — User I/O pin (bank 5)
Pin 90 I/O — User I/O pin (bank 5)
Pin 91 I/O — User I/O pin (bank 5)
Pin 92 I/O — User I/O pin (bank 5)
Pin 93 I/O — User I/O pin (bank 5)
Pin 94 I/O — User I/O pin (bank 5)
Pin 95 VCCINT — Core supply voltage (2.5 V nominal)
Pin 96 VCCINT — Core supply voltage (2.5 V nominal)
Pin 97 GND — Ground
Pin 98 I/O — User I/O pin (bank 6)
Pin 99 I/O — User I/O pin (bank 6)
Pin 100 I/O — User I/O pin (bank 6)
Pin 101 I/O — User I/O pin (bank 6)
Pin 102 I/O — User I/O pin (bank 6)
Pin 103 I/O — User I/O pin (bank 6)
Pin 104 VCCIO6 — I/O bank 6 supply voltage
Pin 105 I/O — User I/O pin (bank 6)
Pin 106 I/O — User I/O pin (bank 6)
Pin 107 GND — Ground
Pin 108 I/O — User I/O pin (bank 6)
Pin 109 I/O — User I/O pin (bank 6)
Pin 110 I/O — User I/O pin (bank 6)
Pin 111 I/O — User I/O pin (bank 6)
Pin 112 I/O — User I/O pin (bank 6)
Pin 113 I/O — User I/O pin (bank 6)
Pin 114 I/O — User I/O pin (bank 6)
Pin 115 VCCINT — Core supply voltage (2.5 V nominal)
Pin 116 VCCINT — Core supply voltage (2.5 V nominal)
Pin 117 GND — Ground
Pin 118 I/O — User I/O pin (bank 7)
Pin 119 I/O — User I/O pin (bank 7)
Pin 120 I/O — User I/O pin (bank 7)
Pin 121 I/O — User I/O pin (bank 7)
Pin 122 I/O — User I/O pin (bank 7)
Pin 123 I/O — User I/O pin (bank 7)
Pin 124 VCCIO7 — I/O bank 7 supply voltage
Pin 125 I/O — User I/O pin (bank 7)
Pin 126 I/O — User I/O pin (bank 7)
Pin 127 GND — Ground
Pin 128 I/O — User I/O pin (bank 7)
Pin 129 I/O — User I/O pin (bank 7)
Pin 130 I/O — User I/O pin (bank 7)
Pin 131 I/O — User I/O pin (bank 7)
Pin 132 I/O — User I/O pin (bank 7)
Pin 133 I/O — User I/O pin (bank 7)
Pin 134 I/O — User I/O pin (bank 7)
Pin 135 VCCINT — Core supply voltage (2.5 V nominal)
Pin 136 VCCINT — Core supply voltage (2.5 V nominal)
Pin 137 GND — Ground
Pin 138 I/O — User I/O pin (bank 8)
Pin 139 I/O — User I/O pin (bank 8)
Pin 140 I/O — User I/O pin (bank 8)
Pin 141 I/O — User I/O pin (bank 8)
Pin 142 I/O — User I/O pin (bank 8)
Pin 143 I/O — User I/O pin (bank 8)
Pin 144 VCCIO8 — I/O bank 8 supply voltage
Pin 145 I/O — User I/O pin (bank 8)
Pin 146 I/O — User I/O pin (bank 8)
Pin 147 GND — Ground
Pin 148 I/O — User I/O pin (bank 8)
Pin 149 I/O — User I/O pin (bank 8)
Pin 150 I/O — User I/O pin (bank 8)
Pin 151 I/O — User I/O pin (bank 8)
Pin 152 I/O — User I/O pin (bank 8)
Pin 153 I/O — User I/O pin (bank 8)
Pin 154 I/O — User I/O pin (bank 8)
Pin 155 VCCINT — Core supply voltage (2.5 V nominal)
Pin 156 VCCINT — Core supply voltage (2.5 V nominal)
Pin 157 GND — Ground
Pin 158 MSEL0 — Configuration mode select 0
Pin 159 MSEL1 — Configuration mode select 1
Pin 160 MSEL2 — Configuration mode select 2
Pin 161 nSTATUS — Configuration status (open-drain)
Pin 162 nCONFIG — Configuration control input (active-low)
Pin 163 CONF_DONE — Configuration done indicator (open-drain)
Pin 164 DCLK — Configuration clock input
Pin 165 DATA0 — Configuration data input 0
Pin 166 nCE — Chip enable (active-low)
Pin 167 nCEO — Chip enable output (active-low, multi-device chain)
Pin 168 VCCINT — Core supply voltage (2.5 V nominal)
Pin 169 GND — Ground
Pin 170 TDI — JTAG test data input
Pin 171 TDO — JTAG test data output
Pin 172 TMS — JTAG test mode select
Pin 173 TCK — JTAG test clock
Pin 174 TRST — JTAG test reset (active-low)
Pin 175 I/O — User I/O pin (bank 8)
Pin 176 I/O — User I/O pin (bank 8)
Pin 177 I/O — User I/O pin (bank 8)
Pin 178 I/O — User I/O pin (bank 8)
Pin 179 I/O — User I/O pin (bank 8)
Pin 180 I/O — User I/O pin (bank 8)
Pin 181 I/O — User I/O pin (bank 8)
Pin 182 I/O — User I/O pin (bank 8)
Pin 183 I/O — User I/O pin (bank 8)
Pin 184 I/O — User I/O pin (bank 8)
Pin 185 I/O — User I/O pin (bank 8)
Pin 186 I/O — User I/O pin (bank 8)
Pin 187 VCCINT — Core supply voltage (2.5 V nominal)
Pin 188 VCCINT — Core supply voltage (2.5 V nominal)
Pin 189 GND — Ground
Pin 190 I/O — User I/O pin (bank 7)
Pin 191 I/O — User I/O pin (bank 7)
Pin 192 I/O — User I/O pin (bank 7)
Pin 193 I/O — User I/O pin (bank 7)
Pin 194 I/O — User I/O pin (bank 7)
Pin 195 I/O — User I/O pin (bank 7)
Pin 196 I/O — User I/O pin (bank 7)
Pin 197 I/O — User I/O pin (bank 7)
Pin 198 I/O — User I/O pin (bank 7)
Pin 199 I/O — User I/O pin (bank 7)
Pin 200 I/O — User I/O pin (bank 7)
Pin 201 I/O — User I/O pin (bank 7)
Pin 202 I/O — User I/O pin (bank 7)
Pin 203 I/O — User I/O pin (bank 7)
Pin 204 I/O — User I/O pin (bank 7)
Pin 205 I/O — User I/O pin (bank 7)
Pin 206 I/O — User I/O pin (bank 7)
Pin 207 I/O — User I/O pin (bank 7)
Pin 208 I/O — User I/O pin (bank 7)
Pin 209 I/O — User I/O pin (bank 7)
Pin 210 I/O — User I/O pin (bank 7)
Pin 211 I/O — User I/O pin (bank 7)
Pin 212 I/O — User I/O pin (bank 7)
Pin 213 I/O — User I/O pin (bank 7)
Pin 214 I/O — User I/O pin (bank 7)
Pin 215 VCCINT — Core supply voltage (2.5 V nominal)
Pin 216 VCCINT — Core supply voltage (2.5 V nominal)
Pin 217 GND — Ground
Pin 218 I/O — User I/O pin (bank 6)
Pin 219 I/O — User I/O pin (bank 6)
Pin 220 I/O — User I/O pin (bank 6)
Pin 221 I/O — User I/O pin (bank 6)
Pin 222 I/O — User I/O pin (bank 6)
Pin 223 I/O — User I/O pin (bank 6)
Pin 224 I/O — User I/O pin (bank 6)
Pin 225 I/O — User I/O pin (bank 6)
Pin 226 I/O — User I/O pin (bank 6)
Pin 227 I/O — User I/O pin (bank 6)
Pin 228 I/O — User I/O pin (bank 6)
Pin 229 I/O — User I/O pin (bank 6)
Pin 230 I/O — User I/O pin (bank 6)
Pin 231 I/O — User I/O pin (bank 6)
Pin 232 I/O — User I/O pin (bank 6)
Pin 233 I/O — User I/O pin (bank 6)
Pin 234 I/O — User I/O pin (bank 6)
Pin 235 I/O — User I/O pin (bank 6)
Pin 236 I/O — User I/O pin (bank 6)
Pin 237 I/O — User I/O pin (bank 6)
Pin 238 I/O — User I/O pin (bank 6)
Pin 239 I/O — User I/O pin (bank 6)
Pin 240 I/O — User I/O pin (bank 6)

Typical Applications

EPF10K130EQC240-1N is suitable for 6 applications: Telecom Interface Cards (T1/E1, Utopia, POS-PHY), Industrial Control and Machine Automation, Legacy PCI/ISA Bus Bridges and Glue Logic, Protocol Converters and Bridge ICs, Mid-Density DSP and Pre/Post-Processing Pipelines, Long-Lifecycle Avionics and Defense Replacement Boards.

🌐

Telecom Interface Cards (T1/E1, Utopia, POS-PHY)

The EPF10K130EQC240-1N fits telecom line-card and backplane designs because of its 186 user I/Os, 64 Kbit of embedded SRAM, and 333.33 MHz internal frequency. Its 2.5 V core and 5 V-tolerant I/O banks allow direct interfacing with legacy 3.3 V/5 V framer ICs, while the FLEX 10KE LAB/EAB architecture implements Utopia Level 2/3 and POS-PHY Level 2/3 PHY interfaces in pure hardware. The 240-pin PQFP footprint also matches the line-card PCB area budget for cPCI/AdvancedTCA mezzanine layouts, and the SRAM configuration supports in-field reprogramming via JTAG for protocol upgrades.

🏭

Industrial Control and Machine Automation

The EPF10K130EQC240-1N is well-suited to PLC backplanes, motor-control interfaces, and CNC machine controllers that demand mid-density glue logic and deterministic timing. Its 832 LABs and 186 I/Os can absorb encoder decoding, PWM generation, and fieldbus glue (Profibus, CANopen, EtherCAT) in a single device, while the 2.5 V core offers reliable operation across industrial temperature environments. The PQFP-240 footprint is friendly to through-hole or socketed industrial backplanes, simplifying field replacement.

🖥️

Legacy PCI/ISA Bus Bridges and Glue Logic

The EPF10K130EQC240-1N excels at replacing dozens of 74-series TTL/MSI logic chips on legacy PCI, ISA, VME, and CompactPCI motherboards. Its 130K gates comfortably absorb bus-arbitration state machines, address-decoding, interrupt controllers, and DMA engines. The 64 Kbit embedded SRAM (4 EABs) provides fast FIFO/buffer storage for bus-master DMA, while the 240-pin PQFP package delivers the 100+ I/Os typically required by multi-master backplane glue logic.

🔧

Protocol Converters and Bridge ICs

The 333.33 MHz internal frequency and dual-port EAB memory of the EPF10K130EQC240-1N make it ideal for protocol converters bridging UART/SPI/I2C to Ethernet, USB-to-legacy-bus, or serial RapidIO-to-PCIe bridges. Its 64 Kbit embedded RAM provides packet-buffer storage for small frames, and the LAB architecture can implement soft UART, SPI, I2C, and even 10/100 Ethernet MAC cores in pure logic. The Pb-free N-suffix finish supports modern lead-free assembly lines used in current production.

📺

Mid-Density DSP and Pre/Post-Processing Pipelines

The EPF10K130EQC240-1N's 4 EAB blocks (8 Kbyte total dual-port memory) make it suitable for FIR/IIR filter pipelines, FFT pre/post-processing, and image-format conversion where modest DSP and FIFO buffering are needed. Its 333 MHz logic performance can sustain video scaling, chroma resampling, or audio-sample-rate conversion at low-to-mid resolutions. The 186 user I/Os allow direct connection to video ADCs/DACs and audio CODECs without intermediate buffers.

✈️

Long-Lifecycle Avionics and Defense Replacement Boards

Although marked Obsolete, the EPF10K130EQC240-1N remains in service on legacy avionics, naval, and ground-defense platforms where 20+ year lifecycle support is mandated. The 240-pin PQFP package is socket-friendly, enabling field replacement without specialized BGA rework. Its mature Quartus II tool flow is well-documented in DO-254/DO-178 evidence packages from prior programs. For new designs in this segment, the EPF10K130EFC484-2 or Cyclone IV GX equivalents are preferred, but the -1N continues to support existing fielded systems.

What is the FLEX 10KE family and what does EPF10K130EQC240-1N do?
The EPF10K130EQC240-1N is a member of Intel's (formerly Altera's) FLEX 10KE family of SRAM-based Field-Programmable Gate Arrays, integrating 130,000 typical system gates and 6,656 logic elements in a 240-pin PQFP package. According to distributor specifications, it delivers 333.33 MHz maximum internal frequency, 186 user I/Os, and 64 Kbit of embedded SRAM across 832 Logic Array Blocks, making it a mid-density reconfigurable logic device. It targets glue logic, bus bridging, and protocol-conversion designs of the early 2000s.
Is the EPF10K130EQC240-1N still in production or obsolete?
The EPF10K130EQC240-1N is currently listed as Obsolete by Arrow Electronics' distributor catalog, indicating Intel has discontinued new production. Verified listings on DigiKey, Mouser, and Octopart remain accessible for legacy stock, but lead-in times may be lengthy and pricing is inventory-driven. For new designs, engineers are advised to migrate to the Cyclone or MAX II families, using this part only for legacy board repair and long-lifecycle maintenance.
What is the difference between EPF10K130EQC240-1N and EPF10K130EQC240-1?
The EPF10K130EQC240-1N adds the N suffix that designates a lead-free (Pb-free) matte-tin finish and lead-free reflow compatibility, whereas the EPF10K130EQC240-1 carries the legacy SnPb lead finish. Both parts share the same -1 speed grade, 240-pin PQFP package, and identical electrical specifications; they are functionally drop-in compatible. Choose the -1N variant for RoHS-compliant assembly, and the -1 for legacy tin-lead assembly processes.
What supply voltage does the EPF10K130EQC240-1N require?
The EPF10K130EQC240-1N operates from a 2.375 V to 2.625 V core supply with a nominal value of 2.5 V, according to the Altera-Micro specification listing. Separate I/O bank supplies may be required if the design interfaces with 3.3 V logic. The 2.5 V rail must be well decoupled with 0.1 µF ceramic and 10 µF bulk capacitors placed close to each VCC pin pair.
How many user I/O pins does the EPF10K130EQC240-1N have?
The EPF10K130EQC240-1N exposes 186 user I/Os across the 240-pin PQFP package, leaving the remaining pins for VCC, GND, JTAG, configuration, and no-connect. According to Kynix specifications, this 186-I/O count is consistent across the FLEX 10KE 240-pin PQFP family. Designers should consult the Quartus pinout file for the exact pin-to-function mapping before PCB layout.
Where can I buy EPF10K130EQC240-1N online today?
The EPF10K130EQC240-1N is available through legacy-stock distributors including DigiKey (part number EPF10K130EQC240-1N-ND), Mouser, Arrow Electronics, and verified brokers listed on Octopart. Because the part is Obsolete per Arrow's catalog, pricing fluctuates with available inventory and lead times may extend beyond 12 weeks. Octopart aggregates real-time stock across multiple distributors, making it the best starting point for sourcing this EOL part.
What is the price of EPF10K130EQC240-1N as of 2026?
As of 2026-09-11, distributor pricing for the EPF10K130EQC240-1N ranges from approximately $145 for single-piece purchases to roughly $88 per unit at 500-piece quantities, based on legacy-stock listings. Prices vary significantly with availability because the part is Obsolete, and brokers may quote higher prices for traceable, date-coded stock. Always verify current pricing directly with the distributor before placing an order, as obsolete-part pricing is highly volatile.
What is the lead time for EPF10K130EQC240-1N orders?
Because the EPF10K130EQC240-1N is listed as Obsolete, lead times are not guaranteed and depend entirely on distributor and broker inventory. Some legacy-stock channels ship immediately from on-hand stock, while special orders may require 8-16 weeks or longer. For new designs with predictable lead time requirements, migrating to a Cyclone II or Cyclone IV equivalent is recommended over relying on obsolete-part supply.
EPF10K130EQC240-1N vs EPF10K50VRC240-4 - which has more logic capacity?
The EPF10K130EQC240-1N offers roughly 2.6× the logic capacity of the EPF10K50VRC240-4, with 6,656 logic elements and 130K gates versus approximately 2,880 logic elements and 50K gates. Both share the 240-pin PQFP package and 2.5 V core supply. Choose the EPF10K130EQC240-1N for designs that exceed 50K gates; the EPF10K50VRC240-4 suffices for smaller glue-logic tasks with simpler state machines and lower I/O counts.
Is there an Altera Cyclone II drop-in replacement for EPF10K130EQC240-1N?
There is no true drop-in pin-compatible Cyclone II replacement for the EPF10K130EQC240-1N because Cyclone II uses TQFP/BGA packages only and runs at 1.2 V core, not 2.5 V. Migration requires PCB redesign with a new footprint and power-rail updates. The closest functional successors are the EP2C35 (in TQFP-144 or BGA packages) for new designs, or another 240-pin FLEX 10KE variant with higher speed grade for legacy SameFrame pin-migration within the same package.
When should I choose EPF10K130EQC240-1N over the EPF10K100EQC240-1N?
Choose the EPF10K130EQC240-1N when your design requires more than 100K gates of logic capacity, as it provides 130K gates and 6,656 logic elements versus the EPF10K100EQC240-1N's 100K gates and approximately 4,992 logic elements. Both parts share the same 240-pin PQFP package and 2.5 V supply, making the -130 a drop-in upgrade. Choose the EPF10K100EQC240-1N for designs that comfortably fit within 100K gates and benefit from reduced power consumption.
What is the best drop-in replacement for the EPF10K130EQC240-1N?
The best drop-in replacement is the EPF10K130EQC240-1 (non-N suffix), which shares the same -1 speed grade, 240-pin PQFP package, and identical electrical performance but carries SnPb lead finish instead of lead-free. For higher performance within the same footprint, the EPF10K130EQC240-2 (one speed grade slower) is also pin-compatible. Cross-brand drop-in replacements do not exist for this Altera-specific FPGA, so the only true drop-ins come from the FLEX 10KE family itself.
Where can I download the EPF10K130EQC240-1N datasheet PDF?
The EPF10K130EQC240-1N datasheet is available as a PDF from multiple aggregator sites including Octopart, Datasheet.Live (pdf.datasheet.live), and Altera-Micro.com, all linking back to the original Intel/Altera FLEX 10KE family datasheet. According to the FLEX 10KE datasheet, the document covers electrical characteristics, pinout, configuration timing, and SameFrame pin-migration guidelines for the entire FLEX 10KE 240-pin PQFP family. Use the Altera-original document for authoritative specifications, since aggregator copies may be partial.
Where do I find the EPF10K130EQC240-1N pinout and package diagram?
The pinout and package diagram for the EPF10K130EQC240-1N are documented in the FLEX 10KE family datasheet, specifically the 240-pin PQFP (240-BFQFP) chapter. According to Partstack's listing, the package code is FQFP (Fine-pitch Quad Flat Pack) with 240 gull-wing terminals. The Quartus II pinout file (.pin or .qsf) generated during compilation provides the exact pin-to-signal assignment for your specific design, which may differ from the default reference pinout.
What is the maximum operating frequency of EPF10K130EQC240-1N?
The maximum internal operating frequency of the EPF10K130EQC240-1N is 333.33 MHz according to multiple distributor listings including Arrow and Kynix. This figure represents the synchronous logic performance for the -1 speed grade; the slower -2 and -3 grades deliver correspondingly lower Fmax values. Real-world achievable frequency depends on routing, fan-out, and design complexity, and is reported in the Quartus slow-model timing report after fitting.
Hey Google, can the EPF10K130EQC240-1N be replaced by a Cyclone FPGA?
No, the EPF10K130EQC240-1N cannot be directly replaced by a Cyclone FPGA on the same PCB because Cyclone devices use different packages (TQFP or BGA, not 240-pin PQFP) and a different core voltage (typically 1.2 V or 1.5 V, not 2.5 V). A board redesign is required to migrate from FLEX 10KE to any Cyclone generation. The closest functional successor with similar logic capacity is the EP2C35 (Cyclone II) or EP3C16 (Cyclone III) in a TQFP-144 package.
What are the key specifications of the EPF10K130EQC240-1N that engineers should know?
Key specifications include 130,000 typical system gates (342,000 maximum), 6,656 logic elements, 832 LABs, 65,536 bits of embedded SRAM organized as four 2,048-bit EABs, 186 user I/Os, 240-pin PQFP package, 2.375-2.625 V core supply, 333.33 MHz maximum internal frequency, SRAM-based configuration memory, lead-free RoHS finish (N suffix), and obsolete lifecycle status per Arrow's catalog. These parameters collectively define the part's logic capacity, I/O bandwidth, power envelope, and long-term availability.

Engineering reference data for EPF10K130EQC240-1N — comparison, design guidance, and compliance information.

Selection Guide

Choose the EPF10K130EQC240-1N when you need the highest-density FLEX 10KE device in a socket-friendly 240-pin PQFP package with lead-free RoHS finish - ideal for telecom interface cards, industrial control boards, and long-lifecycle legacy designs requiring field replacement. Choose the EPF10K130EQC240-1 (non-N) for tin-lead assembly processes or for verified date-code stock. Choose the EPF10K130EQC240-2N or -3N when slower Fmax is acceptable in exchange for lower cost or better availability on the secondary market. Migrate to the EPF10K100EQC240-1N when your design fits within 100K gates and you want to reduce unit cost. For new designs, however, the FLEX 10KE family is obsolete - migrate to Cyclone II/III/IV or MAX II/IV families for long-term availability and tool support.

Comparison with Alternatives

Parameter This Product EPF10K130EQC240-1 EPF10K130EQC240-2N EPF10K130EQC240-3N EPF10K100EQC240-1N EPF10K100EQC240-2N
Package 240-PQFP (32x32 mm) 240-PQFP (32x32 mm) - same 240-PQFP (32x32 mm) - same 240-PQFP (32x32 mm) - same 240-PQFP (32x32 mm) - same 240-PQFP (32x32 mm) - same
Brand Intel (formerly Altera) Intel (formerly Altera) Intel (formerly Altera) Intel (formerly Altera) Intel (formerly Altera) Intel (formerly Altera)
Family FLEX 10KE FLEX 10KE FLEX 10KE FLEX 10KE FLEX 10KE FLEX 10KE
Typical System Gates 130,000 130,000 (identical die) 130,000 (identical die) 130,000 (identical die) 100,000 (-23%) 100,000 (-23%)
Logic Elements 6,656 6,656 (identical) 6,656 (identical) 6,656 (identical) 4,992 (-25%) 4,992 (-25%)
Embedded RAM 64 Kbit (4 × EAB) 64 Kbit 64 Kbit 64 Kbit 49 Kbit (-23%) 49 Kbit (-23%)
User I/Os 186 186 186 186 186 (SameFrame) 186 (SameFrame)
Speed Grade -1 (fastest) -1 (identical) -2 (slower) -3 (slowest) -1 (fastest) -2 (slower)
Lead Finish (N suffix = Pb-free) Pb-free (N suffix) SnPb (legacy) Pb-free Pb-free Pb-free Pb-free

Key Differentiators

  • Highest logic capacity in FLEX 10KE 240-PQFP family (vs EPF10K100EQC240-1N)
  • Fastest speed grade available (-1) (vs EPF10K130EQC240-3N)
  • Pb-free lead finish for modern assembly (vs EPF10K130EQC240-1)

Design Notes

The EPF10K130EQC240-1N requires a clean 2.5 V ±5% (2.375 V to 2.625 V) core supply with high-transient current capability. During configuration, the device can draw peak currents up to 500 mA as it loads the SRAM bitstream. Place 0.1 µF ceramic decoupling capacitors within 5 mm of every VCCINT pin pair, plus 100 µF bulk tantalum or polymer capacitors near the package to suppress the configuration-time inrush. Each VCCIO bank (1-8) needs its own 0.1 µF decoupling capacitor if mixing 3.3 V and 5 V logic levels.

The 240-pin PQFP at 32x32 mm has 0.5 mm pitch leads requiring careful PCB layout: use 0.2 mm trace width with 0.2 mm clearance between pads, and route signals on inner layers to escape the dense outer-lead ring. A 4-layer PCB with continuous ground plane beneath the package is strongly recommended to control impedance and provide a low-inductance return path for the high-toggle-rate I/Os. Leave at least 5 mm of clearance around the PQFP for socket or rework access if the design requires field replacement.

Because the FLEX 10KE family uses SRAM-based configuration, the bitstream must be reloaded on every power-up from a non-volatile source. Use an Altera EPC2LC20N or EPC16 configuration PROM for stand-alone operation, or a microcontroller-driven JTAG (SVF/JIC) load for multi-image or field-updateable designs. Tie nCONFIG high through a 10 kΩ resistor, and ensure CONF_DONE has a 10 kΩ pull-up to VCCIO of the configuration bank. Leave MSEL0/MSEL1/MSEL2 configured for the desired configuration mode (typically AS or PS mode for most designs).

Although FLEX 10KE I/Os are not as fast as modern FPGA I/Os, the 240-pin PQFP lead inductance (~5 nH per lead) can still produce ringing on heavily-loaded outputs. For outputs driving >4 inch traces or >50 pF loads, place 33 Ω series damping resistors at the FPGA pin. For clocks, use the dedicated global clock input pins (CLK0-CLK3) routed through the device's low-skew clock network; avoid using regular I/O pins for clocks as they introduce 1-2 ns of jitter that can degrade setup/hold margins.

Estimated: when migrating from -1 grade to -2 or -3 grades, expect a 15-25% reduction in Fmax and a corresponding drop in design margin. Always re-run Quartus timing analysis after speed-grade change. Another common pitfall is forgetting to verify the configuration mode (AS vs PS) when swapping between EPC2 and EPC16 PROMs - the MSEL pins must match the chosen PROM interface, otherwise CONF_DONE will never assert. Finally, the FLEX 10KE SRAM bitstream is volatile, so always include a configuration device in production builds.

Compliance Information

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Applicable
Lead Free
Yes
Halogen Free
Unknown
Conflict Minerals
Unknown

Pb-free N suffix verified RoHS compliant per Arrow listing. AEC-Q100 not applicable for FPGA used in non-automotive industrial/telecom applications. Halogen-free status and conflict-minerals compliance not explicitly stated in distributor data; default unknown per data authenticity rules.

Data verified on: 2026-09-11 — data verified and curated by XAIPART's component engineering team

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Related Components & Terms

Intel Altera EPF10K130EQC240-1N FLEX 10KE FPGA Field-Programmable Gate Array PQFP 240-BFQFP Logic Array Block (LAB) Embedded Array Block (EAB) SRAM configuration memory Quartus II nCONFIG CONF_DONE JTAG MSEL EPC2LC20N configuration PROM SameFrame pin migration Cyclone II migration path RoHS compliant Pb-free matte-tin finish telemetry interface card industrial control PLC legacy PCI bridge
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