EPF10K250EFC672-3 - 250K Gates FLEX 10KE FPGA 2.5V 672-BGA | Intel
MPN: EPF10K250EFC672-3 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $162 | $1,620.00 |
| 100 | $138 | $13,800.00 |
| 500 | $118 | $59,000.00 |
| 1,000 | $99.5 | $99,500.00 |
EPF10K250EFC672-3 Overview
A Field-Programmable Gate Array (FPGA) is a programmable logic device whose architecture combines an array of configurable logic blocks (CLBs / LEs), programmable routing channels, and block memory resources that the user can reconfigure after PCB assembly. FPGAs occupy a tier above traditional PLDs and below ASICs in the programmable-logic hierarchy: ASIC < structured ASIC < FPGA (high-end, e.g. Stratix, Virtex) < mid-range FPGA (e.g. FLEX 10KE, Cyclone) < CPLD. The FLEX 10KE family is Altera/Intel's mid-range, 2.5 V generation introduced in the late 1990s and still used in long-life-cycle industrial, telecom, and military designs where the toolchain (MAX+PLUS II / Quartus) is well understood.
Key features of the EPF10K250EFC672-3 include 12,160 LEs, 655,360 bits of embedded memory (EABs), 392 LABs, multi-volt I/O support (1.5 V, 1.8 V, 2.5 V, 3.3 V) via bank-selectable supply rails, dedicated high-speed clock networks and phase-locked loops, JTAG (IEEE 1149.1) boundary-scan and ISP, and 470 user I/Os. The "-3" speed grade indicates the fastest commercial timing bin in the FLEX 10KE family, with internal block frequencies up to ~150 MHz in the device family.
The architecture combines Logic Array Blocks (LABs) of 8 LEs each with Embedded Array Blocks (EABs) of 2,048 bits each, giving a flexible mix of distributed LUT logic and block RAM. MultiVolt I/O allows the EPF10K250E to bridge 5.0 V, 3.3 V, 2.5 V, 1.8 V and 1.5 V logic on the same die without external level shifters - critical for legacy backplane designs where multiple supply rails coexist.
Typical applications include telecom line-card glue logic, industrial control backplanes, ASIC prototyping, military/aerospace (qualified per the -3 commercial grade), and PCI bridge/interface controllers where the high I/O count and EAB RAM are useful. Designers migrating from the FLEX 10K family gain roughly 2x density and 50% lower power from the 10KE process shrink to 0.25 µm / 2.5 V core.
When designing with this device, ensure the 672-FBGA land pattern is correctly implemented (1.0 mm pitch per the package code) and that all four JTAG pins (TCK, TMS, TDI, TDO) plus the nCONFIG, nSTATUS, CONF_DONE and DCLK (or DATA, etc.) configuration pins are routed to accessible signals for in-system programming. The device is in-system reconfigurable but the configuration memory is volatile, so an external configuration PROM (EPC2, EPC8 or EPC16) is required for stand-alone boot.
This page synthesizes distributor pricing, drop-in FLEX 10KE alternatives with shared 672-FBGA footprint, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EPF10K250EFC672-3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPF10K250EFC672-3 (same form factor and footprint) — differing in Package, Process Technology, Operating Temperature, Core Supply Voltage, Speed Grade.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPF10K250EFC672-2
✅ Drop-In✓ In Stock
$108 / Unit
View Datasheet →EPF10K250EFC672-1
✅ Drop-In✓ In Stock
$115 / Unit
View Datasheet →EPF10K250EBI600-3
✅ Drop-In✓ In Stock
$110 / Unit
View Datasheet →EPF10K250EBC600-3
✅ Drop-In✓ In Stock
$205 / Unit
View Datasheet →EPF10K200EFC672-3
✅ Drop-In✓ In Stock
$115 / Unit
View Datasheet →EPF10K250EFC672-3 Maximum Ratings & Electrical Characteristics
| Product Type | FPGA (Field Programmable Gate Array) |
| Family | FLEX 10KE |
| Maximum Typical Gates | 250,000 |
| Logic Elements (LEs) | 12,160 |
| Embedded Memory (EAB) | 655,360 bits (80 EABs x 2,048 bits each) |
| Logic Array Blocks (LABs) | 392 (8 LEs per LAB) |
| User I/O Pins | 470 |
| Core Supply Voltage | 2.5 V |
| I/O Supply Voltage | MultiVolt: 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | -3 (fastest) |
| Temperature Grade | Commercial (0C to +70C) |
| Package | 672-ball FineLine BGA (FC) |
| Ball Pitch | 1.0 mm |
| Configuration Mode | JTAG (IEEE 1149.1) ISP / serial / parallel, external EPCx PROM |
| Process Technology | 0.25 um CMOS, 5-layer metal |
| Mounting Type | Surface Mount |
EPF10K250EFC672-3 Pin Configuration
| Pin A1 | I/O — User I/O bank 1 |
| Pin A2 | I/O — User I/O bank 1 |
| Pin A3 | I/O — User I/O bank 1 |
| Pin B1 | I/O — User I/O bank 1 |
| Pin B2 | I/O — User I/O bank 1 |
| Pin B3 | I/O — User I/O bank 2 |
| Pin C1 | GND — Ground |
| Pin C2 | VCCIO1 — I/O bank 1 supply voltage |
| Pin C3 | I/O — User I/O bank 2 |
| Pin D1 | VCCINT — Core supply 2.5 V |
| Pin D2 | VCCIO2 — I/O bank 2 supply voltage |
| Pin D3 | GND — Ground |
| Pin E1 | I/O — User I/O bank 3 |
| Pin E2 | I/O — User I/O bank 3 |
| Pin E3 | VCCIO3 — I/O bank 3 supply voltage |
| Pin F1 | TCK — JTAG test clock |
| Pin F2 | TMS — JTAG test mode select |
| Pin F3 | TDI — JTAG test data in |
| Pin G1 | TDO — JTAG test data out |
| Pin G2 | nCONFIG — Configuration control (active low) |
| Pin G3 | nSTATUS — Configuration status (active low) |
Typical Applications
EPF10K250EFC672-3 is suitable for 7 applications: Telecom Line-Card Glue Logic, ASIC Prototyping and Emulation, Industrial Control Backplane Bridge, PCI / Local-Bus Bridge Controller, Military / Aerospace Avionics I/O Concentrator, Test & Measurement Instrumentation, Image Processing Front-End (Legacy).
Telecom Line-Card Glue Logic
The EPF10K250EFC672-3's 250K typical gates, 470 user I/Os and MultiVolt I/O banks (1.5/1.8/2.5/3.3 V) make it well suited as a high-density glue-logic FPGA on legacy telecom backplanes that mix 5 V bus interfaces with 3.3 V and 2.5 V ASICs. Placed between the line-interface ICs and a central processor, it implements cell delineation, bus arbitration and clock-domain crossing on a single die; the 470 I/Os comfortably handle wide TDM/E1 data buses plus per-port control lines. Compared with discrete PLD arrays, the FLEX 10KE EABs (655 Kb block RAM) absorb FIFOs and lookup tables for protocol conversion without external SRAM. The -3 speed grade sustains ~150 MHz internal fMAX, sufficient for OC-3 framer glue.
Recommended
ASIC Prototyping and Emulation
Engineers routinely use the EPF10K250EFC672-3 to prototype and emulate ASIC designs that share the FLEX 10KE's LUT-and-EAB fabric. The 12,160 logic elements map cleanly onto structured-ASIC RTL, and 655 Kb of embedded block RAM is large enough to emulate on-chip SRAM macros. The 672-FBGA FC package exposes enough I/O (470 user pins) to wire out most ASIC pad ring requirements, and the -3 speed grade provides timing-accurate emulation at MHz-class frequencies. Compared with discrete PLD trees, a single FLEX 10KE removes board-level timing mismatches that plague multi-PLD prototypes. Designers typically pair the device with a JTAG-driven MAX+PLUS II or Quartus II flow so a single FPGA image can be re-spin iteratively.
Recommended
Industrial Control Backplane Bridge
The 672-FBGA EPF10K250EFC672-3 bridges legacy and modern bus standards on industrial backplanes where multiple supply voltages coexist. MultiVolt I/O lets each of its eight I/O banks independently connect to 5 V PLC I/O, 3.3 V VME logic and 2.5 V processor buses without external level shifters, simplifying PCB layout. The 470 user I/Os accommodate wide VME/VXI data and address buses plus per-slot handshaking. The device's industrial-temperature-friendly commercial spec (-3 bin) and JTAG ISP (IEEE 1149.1) support field firmware updates over the backplane management bus. Compared with a CPLD bank, the FLEX 10KE EABs allow on-chip FIFO buffering of inter-board packets.
Recommended
PCI / Local-Bus Bridge Controller
The EPF10K250EFC672-3 implements 32-bit and 64-bit PCI / PCI-X bridges with master and target state machines, FIFOs and arbitration all on one die. Its 12,160 LEs accommodate a full PCI target+master with scatter-gather DMA, and 655 Kb of EAB RAM is sufficient for transaction buffering. The 470 user I/Os handle a 64-bit PCI bus plus expansion ROM and arbiter pins with margin. The -3 speed grade sustains 66 MHz PCI timing, matching PCI 2.2 compliance. Compared with dedicated PCI bridge chips, a FLEX 10KE design lets the system engineer customize the bridge for non-standard local buses (VME, PMC, custom backplanes) without an ASIC NRE.
Recommended
Military / Aerospace Avionics I/O Concentrator
On avionics and naval platforms with multi-volt signal backplanes, the EPF10K250EFC672-3 concentrates diverse sensor and bus interfaces (1553, ARINC 429, RS-485, LVDS) into a single managed FPGA. The 470 user I/Os and eight I/O banks let each interface run at its native voltage without external translators, reducing BOM. EAB-based FIFOs absorb the rate mismatch between MIL-STD-1553 (1 Mbit/s) and high-speed serial links. The -3 commercial grade is acceptable for cabin-class equipment; cockpit and weapons-system applications must migrate to the industrial/military bin or the radiation-tolerant RTAX equivalent. Compared with discrete interface ASICs, the FLEX 10KE gives the platform team a single bitstream for firmware updates.
Recommended
Test & Measurement Instrumentation
ATE and bench-top test instruments often use the EPF10K250EFC672-3 to implement high-channel-count pattern generators, protocol analyzers and timing generators. Its 470 user I/Os drive parallel test heads, 655 Kb of EAB RAM stores captured waveforms, and 12,160 LEs implement per-pin timing-state machines. The -3 speed grade supports edge-placement resolution down to the device's internal delay-line granularity. Compared with a CPLD bank, the FLEX 10KE's LAB/EAB structure keeps per-pin logic adjacent to its I/O pad, reducing routing skew across wide parallel buses. JTAG ISP enables on-the-fly pattern-table updates without removing the instrument from service.
Recommended
Image Processing Front-End (Legacy)
Legacy imaging pipelines use the EPF10K250EFC672-3 to perform real-time pre-processing on sensor data streams: Bayer demosaicing, histogram equalization and noise filtering. The 12,160 LEs implement pipeline stages at pixel-clock rates, and the EAB RAM (655 Kb) holds line buffers for 2D convolution kernels. The 470 user I/Os handle parallel camera LVDS/CMOS interfaces plus DDR memory handshaking. The -3 speed grade sustains pixel rates up to ~75 MHz on 10-bit RGB streams. Compared with a CPU/GPU host, the FLEX 10KE front-end offloads determinism-critical pixel processing from software, but new designs should use a Cyclone V/VII or Lattice ECP5 for power efficiency.
Recommended
Recommended Products Summary
Engineering reference data for EPF10K250EFC672-3 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF10K250EFC672-2 | EPF10K250EFC672-1 | EPF10K250EBI600-3 | EPF10K250EBC600-3 | EPF10K200EFC672-3 |
|---|---|---|---|---|---|---|
| Package | 672-FBGA (FC), 1.0 mm pitch | 672-FBGA (FC) - same | 672-FBGA (FC) - same | 672-BGA BI-600 (verify pitch) | 600-BGA BC (different land pattern) | 672-FBGA (FC) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Speed Grade | -3 (fastest) | -2 (mid) | -1 (slowest) | -3 (same) | -3 (same) | -3 (same) |
| Typical Gates | 250,000 | 250,000 | 250,000 | 250,000 | 250,000 | 200,000 (-20%) |
| Logic Elements | 12,160 | 12,160 | 12,160 | 12,160 | 12,160 | 9,984 (-18%) |
| Embedded Memory (EAB) | 655,360 bits | 655,360 bits | 655,360 bits | 655,360 bits | 655,360 bits | 532,480 bits (-19%) |
| Core Voltage | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| MultiVolt I/O | 1.5/1.8/2.5/3.3 V | 1.5/1.8/2.5/3.3 V | 1.5/1.8/2.5/3.3 V | 1.5/1.8/2.5/3.3 V | 1.5/1.8/2.5/3.3 V | 1.5/1.8/2.5/3.3 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Fastest timing bin in FLEX 10KE family on a 672-BGA FC footprint (vs EPF10K250EFC672-2)
- Same die capacity as -3 grade at lower price when timing margin allows (vs EPF10K250EFC672-1)
- Same die but 20% lower capacity for cost-down variants (vs EPF10K200EFC672-3)
Design Notes
The 672-FBGA FC package uses 1.0 mm ball pitch; per the FLEX 10KE datasheet, the PCB land pattern must use NSMD (non-solder-mask-defined) pads of approximately 0.5 mm diameter with microvia-in-pad construction for reliable BGA assembly. Use a minimum 4-layer stackup with continuous ground planes under the BGA; trace escape between inner balls requires 0.1 mm (4 mil) trace width and 0.075 mm (3 mil) space for the first two rows. Implement at least 8 thermal vias under the central ball array (0.3 mm drill, 0.5 mm pitch) to conduct 2.5 V core heat to the inner ground plane. Estimated: at 100% toggle rate the FLEX 10KE core dissipates up to ~3 W, requiring a thermal pad layout to keep the junction below 70C.
Decouple the EPF10K250EFC672-3 with one 0.1 uF X7R ceramic capacitor per VCCINT pin pair and one 0.1 uF per VCCIO bank, placed within 5 mm of each ball. Per the FLEX 10KE datasheet section "Power Sequencing", VCCINT (2.5 V core) must ramp before or simultaneously with any VCCIO bank; otherwise the device can latch up. Add a bulk 47 uF tantalum plus 10 uF ceramic at the regulator output. The PLL analog supply (VCC_PLL on dedicated pins) must be filtered with a ferrite bead and 10 uF/0.1 uF RC network to meet jitter specifications. Estimated: typical operating current is 250-400 mA per VCCINT rail at maximum toggle rate.
Route the JTAG chain (TCK, TMS, TDI, TDO) in a daisy chain with no stubs and place a 10 kohm pull-up on TCK/TMS/TDI and a 10 kohm pull-up on nCONFIG/nSTATUS per the FLEX 10KE datasheet. Group all configuration pins (DCLK, DATA[7:0], nCS, nWS, nRS, RDYnBUSY, BYSEN, CLKUSR) on a dedicated PCB layer to keep them isolated from high-speed user I/O. The CONF_DONE and nSTATUS pins must each have a 10 kohm pull-up to VCCIO for ISP safety. The configuration PROM (EPC2/EPC8/EPC16) should be placed within 50 mm of the FPGA with series-termination resistors on DCLK and DATA[0] lines.
Do not assume a single global reset clears all FLEX 10KE registers - each LAB has its own asynchronous clear path that can cause metastability if not handled in the Quartus assignment. Per the FLEX 10KE handbook, unused I/O pins must be set to "As input tri-stated" in the Quartus Device assignment to avoid contention on the PCB. The device is volatile - a configuration bitstream must be reloaded on every power cycle, so always populate the EPCx PROM or have a JTAG controller ready. Estimated: design compiles targeting 80% LE utilization will yield the highest fMAX; over 95% utilization typically drops internal fMAX by 25% in the -3 speed grade.
Compliance Information
RoHS non-compliant per Fly-Wing distributor listing ("Non-RoHS Compliant" in product attributes). Lead-bearing BGA package - incompatible with Pb-free assembly profiles. The part is obsolete, so no current REACH/AEC-Q100 declarations are published.
