Altera

EPF6016ATC144-1 - FLEX 6000 FPGA, 16K Gates, 1320 Cells, 144-LQFP | Altera (Intel)

MPN: EPF6016ATC144-1 ✗ End of Life

In Stock Ships in 1-3 business days

3.3 V Vdss 144-LQFP (TQFP) Package -1 (slowest) Speed

From $9.95 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$18.5	$18.50
10	$16.2	$162.00
100	$13.85	$1,385.00
500	$11.4	$5,700.00
1,000	$9.95	$9,950.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

EPF6016ATC144-1 Overview

The Altera (Intel) EPF6016ATC144-1 is a member of the FLEX 6000 family of SRAM-based Field Programmable Gate Arrays, integrating 16,000 typical gates and 1,320 logic cells into a 144-pin LQFP (Low-profile Quad Flat Pack) surface-mount package. The device uses 0.42 µm CMOS SRAM process technology, operates from a 3.3 V core supply, and supports user I/O voltages tolerant to 5.0 V, enabling glueless interface to legacy 5 V peripherals. The 'ATC' speed grade and '1' device suffix designate the slowest of three speed grades offered in the family, optimized for low power rather than maximum toggle rate.

An FPGA (Field Programmable Gate Array) is a semiconductor device containing an array of configurable logic blocks (CLBs) connected by programmable interconnect, allowing designers to implement arbitrary digital logic without fabricating a custom ASIC. The FLEX 6000 family is positioned as a low-cost alternative to gate-array ASICs and is well suited to glue logic, bus bridging, and state-machine replacement on volume production boards where full Custom IC development cost is unjustified.

Key features include 1,320 logic elements organized into 132 Logic Array Blocks (LABs), 117 user I/Os, built-in JTAG boundary-scan support, and four low-skew global clock networks. The EPF6016ATC144-1 also provides tri-state buffer control on every I/O, support for MultiVolt I/O interfacing, and configurability via serial or parallel EPROM/Flash configuration devices.

Architecturally, the FLEX 6000 device uses an enhanced continuous-channel routing interconnect combined with four dedicated carry chains per LAB for high-speed arithmetic. The continuous routing architecture minimizes interconnect delay variance, allowing designers to predict worst-case propagation delay more reliably than segmented architectures.

Typical applications include telecommunications line cards, industrial control glue logic, peripheral bus bridges, and low-volume ASIC replacement. The wide I/O count (117) suits 32-bit datapath bridges and address-decoding functions.

When designing with this device, verify the configuration scheme (passive serial, active serial, or JTAG) and confirm ByteBlaster/MasterBlaster support in the Quartus MAX+PLUS II toolchain. Note that this part is end-of-life per Intel PSG.

This page synthesizes distributor pricing, drop-in alternatives from the FLEX 6000 family and equivalent XAIPART-listed MPNs, and practical design notes not found in the legacy Altera datasheet.

Drop-in alternatives for EPF6016ATC144-1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF6016ATC144-1 (same form factor and footprint) — differing in Package, Process Technology, Operating Temperature, Speed Grade, Configuration Method.

EPF6016AT1144-3N

Altera

Package: TQFP-144 (T144) 22x22 mm

Speed Grade: -3 (commercial)

Configuration Method: JTAG / ByteBlasterMV / BitBlaster with external EPC2 or EPC1441 PROM