EPF6016ATC144-3S - FLEX 6000 FPGA, 132 LABs, 117 IOs | Intel
MPN: EPF6016ATC144-3S ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.75 | $2,875.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $18.1 | $18,100.00 |
EPF6016ATC144-3S Overview
A Field Programmable Gate Array (FPGA) is a type of integrated circuit that can be configured by the customer or designer after manufacturing, hence the term field-programmable. The FLEX 6000 family sits within Intel's programmable logic hierarchy between simpler Complex Programmable Logic Devices (CPLDs) and higher-density FPGAs such as the FLEX 10K and APEX families. FPGAs in general belong to the broader semiconductor taxonomy of Programmable Logic Devices (PLDs), which also include SPLDs and CPLDs. They are widely used for digital logic prototyping, glue logic, custom I/O interfacing, and pre-ASIC design verification where production volumes do not yet justify a mask-programmed gate array.
The EPF6016ATC144-3S is specified as commercial grade with an operating temperature range of 0°C to 85°C and operates from a 5.0 V supply. The trailing S in the order code denotes a specific Altera/Intel ordering suffix (often indicating a particular shipment form or speed/packaging variant), while the -3 speed grade denotes the -3 performance bin within the FLEX 6000 family. The part supports in-system programmability via the IEEE 1149.1 (JTAG) boundary-scan interface and is configured via a serial configuration device.
Typical applications for the EPF6016ATC144-3S include glue logic in telecom infrastructure, industrial control and factory automation I/O expansion, PCI bus interface bridging, custom peripheral controllers in embedded systems, and pre-ASIC prototyping where design teams need to validate RTL prior to tape-out. The 117 available user I/Os make the device well-suited to bridging legacy 5 V peripherals to modern ASICs or microprocessors.
When designing with this part, ensure that all 5 V supply rails are properly decoupled with 0.1 µF ceramic capacitors placed within 5 mm of each VCC pin, and that JTAG chain integrity is verified before configuration. The device is now considered legacy/NRND: production of the FLEX 6000 family has largely ended, and Intel recommends migrating to Cyclone-series devices for new designs.
This page synthesizes distributor pricing, drop-in package-compatible variants from the same FLEX 6000 family, and practical design notes not found on a single distributor page.
Drop-in alternatives for EPF6016ATC144-3S — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPF6016ATC144-3S (same form factor and footprint) — differing in Package, Configuration Method, Operating Temperature, Process Technology, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPF6016ATC144-3N
✅ Drop-In✓ In Stock
$12.4 / Unit
View Datasheet →EPF6016ATC144-3
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EPF6016ATC144-2N
✅ Drop-In✓ In Stock
$19.5 / Unit
View Datasheet →EPF6016ATC144-2
✅ Drop-In✓ In Stock
$13.85 / Unit
View Datasheet →EPF6016ATC144-1
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EPF6016ATC144-3S Maximum Ratings & Electrical Characteristics
| Family | FLEX 6000 |
| Typical Gates | 16,000 |
| Maximum System Gates | 24,000 |
| Logic Elements | 1,320 |
| Logic Array Blocks (LABs) | 132 |
| User I/Os | 117 |
| Internal Frequency (max) | 172 MHz |
| Package | 144-pin TQFP (TQFP-144) |
| Supply Voltage (VCCINT) | 5.0 V |
| Process Technology | 0.42 µm CMOS SRAM |
| Operating Temperature | 0 °C to +85 °C (commercial) |
| Speed Grade | -3 |
| Configuration Interface | JTAG (IEEE 1149.1) + serial configuration device |
| Mounting Type | Surface Mount |
EPF6016ATC144-3S Pin Configuration
| Pin 1 | I/O — User I/O pin |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | VCCINT — 5.0 V core supply |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | GND — Ground |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | VCCIO — I/O supply voltage |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | GND — Ground |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | VCCINT — 5.0 V core supply |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | GND — Ground |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | VCCIO — I/O supply voltage |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | GND — Ground |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | VCCINT — 5.0 V core supply |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | GND — Ground |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | VCCIO — I/O supply voltage |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | GND — Ground |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | VCCINT — 5.0 V core supply |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | GND — Ground |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | VCCIO — I/O supply voltage |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | TDI — JTAG Test Data In |
| Pin 74 | TMS — JTAG Test Mode Select |
| Pin 75 | TCK — JTAG Test Clock |
| Pin 76 | TDO — JTAG Test Data Out |
| Pin 77 | nCONFIG — Configuration control |
| Pin 78 | nSTATUS — Configuration status |
| Pin 79 | CONF_DONE — Configuration done |
| Pin 80 | DCLK — Configuration clock |
| Pin 81 | DATA0 — Configuration data input |
| Pin 82 | MSEL1 — Configuration mode select 1 |
| Pin 83 | MSEL0 — Configuration mode select 0 |
| Pin 84 | nCE — Chip enable (active low) |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | I/O — User I/O pin |
| Pin 87 | I/O — User I/O pin |
| Pin 88 | GND — Ground |
| Pin 89 | I/O — User I/O pin |
| Pin 90 | I/O — User I/O pin |
| Pin 91 | I/O — User I/O pin |
| Pin 92 | VCCINT — 5.0 V core supply |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | GND — Ground |
| Pin 97 | I/O — User I/O pin |
| Pin 98 | I/O — User I/O pin |
| Pin 99 | I/O — User I/O pin |
| Pin 100 | I/O — User I/O pin |
| Pin 101 | VCCIO — I/O supply voltage |
| Pin 102 | I/O — User I/O pin |
| Pin 103 | I/O — User I/O pin |
| Pin 104 | I/O — User I/O pin |
| Pin 105 | I/O — User I/O pin |
| Pin 106 | GND — Ground |
| Pin 107 | I/O — User I/O pin |
| Pin 108 | I/O — User I/O pin |
| Pin 109 | I/O — User I/O pin |
| Pin 110 | I/O — User I/O pin |
| Pin 111 | VCCINT — 5.0 V core supply |
| Pin 112 | I/O — User I/O pin |
| Pin 113 | I/O — User I/O pin |
| Pin 114 | I/O — User I/O pin |
| Pin 115 | I/O — User I/O pin |
| Pin 116 | GND — Ground |
| Pin 117 | I/O — User I/O pin |
| Pin 118 | I/O — User I/O pin |
| Pin 119 | I/O — User I/O pin |
| Pin 120 | I/O — User I/O pin |
| Pin 121 | VCCIO — I/O supply voltage |
| Pin 122 | I/O — User I/O pin |
| Pin 123 | I/O — User I/O pin |
| Pin 124 | I/O — User I/O pin |
| Pin 125 | I/O — User I/O pin |
| Pin 126 | GND — Ground |
| Pin 127 | I/O — User I/O pin |
| Pin 128 | I/O — User I/O pin |
| Pin 129 | I/O — User I/O pin |
| Pin 130 | I/O — User I/O pin |
| Pin 131 | VCCINT — 5.0 V core supply |
| Pin 132 | I/O — User I/O pin |
| Pin 133 | I/O — User I/O pin |
| Pin 134 | I/O — User I/O pin |
| Pin 135 | GND — Ground |
| Pin 136 | I/O — User I/O pin |
| Pin 137 | I/O — User I/O pin |
| Pin 138 | I/O — User I/O pin |
| Pin 139 | I/O — User I/O pin |
| Pin 140 | VCCIO — I/O supply voltage |
| Pin 141 | I/O — User I/O pin |
| Pin 142 | I/O — User I/O pin |
| Pin 143 | I/O — User I/O pin |
| Pin 144 | I/O — User I/O pin |
Typical Applications
EPF6016ATC144-3S is suitable for 6 applications: Telecom Glue Logic and Bus Bridging, Industrial Control and Factory Automation I/O Expansion, PCI Bridge and Legacy Peripheral Controllers, Pre-ASIC RTL Prototyping and Emulation, Custom Avionics Display and Sensor Interface (Legacy), Educational FPGA Lab and University Coursework.
Telecom Glue Logic and Bus Bridging
The EPF6016ATC144-3S fits telecom backplane glue-logic and bus-bridging applications because its 117 user I/Os and 132 LABs (1,320 LEs) can absorb multiple small peripheral controllers and protocol-conversion state machines in a single device. The 5.0 V tolerant I/O banks interface directly to legacy TTL peripherals on telecom line cards without level-shifters. Compared with a CPLD, the FLEX 6000 fabric offers more headroom for state-rich bridging logic (for example, between an MPC860 host and an HDLC framer) while keeping the JTAG-based configuration flow familiar to telecom firmware teams. Trade-off: this family is NRND, so production designs should plan a Cyclone migration path with the PCB layout adjusted for the new footprint.
Recommended
Industrial Control and Factory Automation I/O Expansion
In factory automation, the EPF6016ATC144-3S is well suited to expand a PLC or industrial PC's parallel I/O count by mapping encoder inputs, opto-isolated 24 V field signals, and PWM outputs through its 117 I/O pins. The -3 speed grade's 172 MHz internal frequency is more than adequate for deterministic machine-control state machines running at microsecond loop times. The TQFP-144 surface-mount package is easy to assemble on industrial SBCs that need to survive 0–85 °C commercial environments with adequate derating. Note that the FLEX 6000 family is NRND, so new industrial designs should evaluate Cyclone IV or Cyclone 10 LP for long-term supply continuity.
Recommended
PCI Bridge and Legacy Peripheral Controllers
The EPF6016ATC144-3S's 1,320 logic elements and 117 I/Os have historically been used to implement 32-bit PCI bus bridges, custom DMA engines, and ISA-to-PCI protocol converters in embedded SBC designs. Its 172 MHz internal Fmax comfortably meets the 33 MHz PCI clock domain with margin for state-machine pipelines. The 5 V tolerant I/O banks connect directly to legacy ISA and PCI buses that still use 5 V signaling. For new designs the same architectural role should be filled by a Cyclone-series device, but in service and refurbishment contexts the FLEX 6000 remains a drop-in for legacy motherboards.
Recommended
Pre-ASIC RTL Prototyping and Emulation
Design teams historically chose the EPF6016ATC144-3S to validate RTL blocks before committing to an ASIC mask set, because FLEX 6000 design entry with Quartus II allows fast compile-and-test cycles at moderate logic density. The 16,000 typical gates accommodate control-plane state machines, FIFO controllers, memory interfaces, and glue for soft-IP cores in a single chip. The JTAG (IEEE 1149.1) configuration path enables rapid board-level bring-up and incremental bitstream updates. While modern ASIC prototyping typically uses Cyclone, Stratix, or external emulators, EPF6016ATC144-3S boards remain in service at universities and small consultancies for low-cost FPGA education.
Recommended
Custom Avionics Display and Sensor Interface (Legacy)
Although not AEC-Q100 qualified, the EPF6016ATC144-3S was used in some legacy avionics subsystems where commercial-grade FPGAs were acceptable for non-flight-critical display drivers, sensor-format conversion, and ARINC-429 bridges. The 117 I/Os could absorb multiple ARINC-429 channels plus display timing logic, and the 5 V I/O compatibility simplified interfacing with older cockpit displays. New avionics programs must use AEC-Q100 qualified parts (such as certain Microsemi/PolarFire devices), so this use case is limited to maintenance of legacy systems. The -3 speed grade's 172 MHz Fmax easily meets display pixel-clock and ARINC-429 bit-rate requirements.
Recommended
Educational FPGA Lab and University Coursework
Universities still deploy EPF6016ATC144-3S-based development boards for introductory digital-logic and computer-architecture courses because the FLEX 6000 architecture is well documented in textbooks, and Quartus II Web Edition supports the family in legacy versions. The 132 LABs and 117 I/Os give students enough logic capacity to implement CPUs, peripherals, and SoC prototypes on a single chip. The TQFP-144 package is breadboard-friendly with 0.5 mm pitch adapters. The trade-off is that Quartus II versions supporting FLEX 6000 are no longer maintained, so students may need a virtual machine with legacy software to compile bitstreams.
Recommended
Recommended Products Summary
Engineering reference data for EPF6016ATC144-3S — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF6016ATC144-3N | EPF6016ATC144-3 | EPF6016ATC144-2N | EPF6016ATC144-2 | EPF6016ATC144-1 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-144 | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) |
| Family | FLEX 6000 | FLEX 6000 | FLEX 6000 | FLEX 6000 | FLEX 6000 | FLEX 6000 |
| Speed Grade | -3 | -3 (same) | -3 (same) | -2 (slower) | -2 (slower) | -1 (slowest) |
| Logic Array Blocks (LABs) | 132 | 132 | 132 | 132 | 132 | 132 |
| Logic Elements | 1,320 | 1,320 | 1,320 | 1,320 | 1,320 | 1,320 |
| User I/Os | 117 | 117 | 117 | 117 | 117 | 117 |
| Operating Temperature | 0 °C to +85 °C (commercial) | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Same 132 LAB/1,320 LE die across all alternatives (vs EPF6016ATC144-2N)
- TQFP-144 footprint fully preserved across speed grades (vs EPF6016ATC100-3)
- Ordering suffix S vs N vs blank does not change pinout (vs EPF6016ATC144-3N)
Design Notes
Estimated: at 100 MHz toggle rate and 50 % I/O switching on a fully utilized 117-I/O design, the EPF6016ATC144-3S core plus I/O supply current can exceed 250 mA from the 5.0 V VCCINT rail. Provide at least four 0.1 µF X7R ceramic decoupling capacitors placed within 5 mm of the VCCINT/VCCIO pins, plus a bulk 47 µF tantalum or polymer capacitor on the supply rail. The VCCINT and VCCIO planes should be split to allow independent regulation; VCCIO may be set to 3.3 V or 5.0 V depending on the peripheral logic level.
The TQFP-144 package has a 0.5 mm lead pitch and a 20 × 20 mm body, which is straightforward to route on a 4-layer PCB with 0.2 mm trace/space. Place a continuous ground plane on layer 2 directly beneath the device to provide a low-impedance return path for the 117 high-speed I/Os. Keep configuration and JTAG traces (TDI, TMS, TCK, TDO, nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA0) short, and add 10 kΩ pull-ups on nCONFIG and pull-downs on nSTATUS per the FLEX 6000 configuration guide.
Do not assume the EPF6016ATC144-3S can be substituted with a Cyclone device on the same PCB layout — the pinouts differ and the I/O voltage topology has changed. Quartus II versions newer than 13.0sp1 do not support the FLEX 6000 family; use Quartus II 9.1 or 13.0sp1 to compile bitstreams. Also verify CONFIG_DONE rises cleanly at power-up, otherwise the device will remain in configuration mode and all user I/Os stay tri-stated.
Compliance Information
RoHS and lead-free status for the EPF6016ATC144-3S are not confirmed in the verified distributor data and are marked [DATA_NEEDED]. The part is commercial-grade (0–85 °C) and is not AEC-Q100 qualified. Intel's Conflict Minerals Reporting Template applies to all FPGA product lines.