Intel

EPF6024AQC240-4N - FLEX 6000 FPGA, 24K Gates | Intel (Altera)

Name: EPF6024AQC240-4N - FLEX 6000 FPGA, 24K Gates | Intel (Altera)
Brand: Intel
SKU: EPF6024AQC240-4N
Price: 9.2 USD
Availability: InStock

MPN: EPF6024AQC240-4N ✗ End of Life

In Stock Ships in 1-3 business days

3.3 V Vdss PQFP-240 (240-pin PowerQuad Flat Package) Package up to 172 MHz Speed

From $9.2 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$18.5	$18.50
10	$15.2	$152.00
100	$12.8	$1,280.00
500	$10.5	$5,250.00
1,000	$9.2	$9,200.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EPF6024AQC240-4N Overview

The Intel (formerly Altera) EPF6024AQC240-4N is a member of the FLEX 6000 family of CMOS SRAM-based Field-Programmable Gate Arrays (FPGAs), providing up to 24,000 typical gates in a 240-pin PowerQuad Flat Package (PQFP-240). The "-4" speed grade denotes the fastest available in the family, and the "N" suffix indicates a lead-free / Pb-free finish. The FLEX 6000 family uses a fine-grained Look-Up Table (LUT) architecture with continuous routing and OptiFLEX expansion, targeting low-cost, high-volume programmable logic designs where fast design changes during prototyping are required.

An FPGA (Field-Programmable Gate Array) is a type of programmable logic device (PLD) that lets designers configure digital logic through a four-step flow (design entry, place-and-route, simulation, programming) without fabricating a custom ASIC. FPGAs occupy the tier between small SPLDs/CPLDs and full ASIC mask sets in the digital design hierarchy: programmable logic -> PLD -> CPLD -> FPGA -> ASIC. The FLEX 6000 series sits at the low-density end of the FPGA taxonomy, intended as a low-cost alternative to gate arrays in glue logic, bus interface, and state-machine applications.

Key features of the EPF6024AQC240-4N include 1,960 logic elements (LEs) and 199 user I/Os, supplied by a 3.3 V core supply with 5 V-tolerant I/O. The device is configured via the IEEE 1149.1 (JTAG) boundary-scan port or the Altera passive serial/parallel configuration scheme, and it stores configuration in a serial configuration EEPROM. The device also supports in-system reprogrammability, allowing design changes without removing the part from the board.

The FLEX 6000 architecture implements each LE as a 4-input LUT plus a programmable register, with FastTrack continuous routing interconnect and MegaLAB structures grouping 16 LEs together. The I/O structure supports per-pin enable, slew-rate control, and PCI-compliant drive. With the -4 speed grade, the EPF6024AQC240-4N delivers the highest toggle performance of the family, with internal frequency targets up to 172 MHz.

Typical applications include bus-interface bridges (e.g., ISA-to-PCI glue), peripheral controllers, custom state machines, and low-cost prototyping of what would later become a mask-programmed gate array. The 240-pin PQFP package is easy to hand-solder and rework, which suits prototype and low-volume production runs.

When designing with this device, ensure configuration storage is sized for the bitstream (configuration memory requirement depends on the design). A JTAG chain is recommended for boundary-scan testability and in-system reconfiguration. Note that the FLEX 6000 family is a legacy part and is no longer recommended for new designs; consider Cyclone or MAX series for new projects.

This page synthesizes distributor pricing, same-package drop-in alternatives from the FLEX 6000 family, and practical design notes not found in the manufacturer datasheet.

Drop-in alternatives for EPF6024AQC240-4N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF6024AQC240-4N (same form factor and footprint) — differing in Package, Speed Grade, Configuration Method, Device Type, Process Technology.

EPF6024AQC240-1N

Intel

Package: 240-pin PQFP (BFQFP)

Device Type: FPGA (Field Programmable Gate Array)

Process Technology: 0.42 µm CMOS