EP1M350F780I5N - Mercury PLD FPGA, 350K Gates, 780 FBGA | Altera
MPN: EP1M350F780I5N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $235 | $23,500.00 |
| 500 | $210 | $105,000.00 |
| 1,000 | $195 | $195,000.00 |
EP1M350F780I5N Overview
A Programmable Logic Device (PLD) is a digital semiconductor whose logic function is defined by the customer after manufacture, sitting in the broader taxonomy of Field-Programmable Gate Arrays (FPGAs) and Complex PLDs (CPLDs). PLDs are used to implement arbitrary digital logic, glue logic, state machines, and datapath functions without fabricating a custom chip. The Mercury PLD architecture combines look-up table (LUT)-based logic with embedded high-speed transceivers, dedicated clock management, and dual-port SRAM blocks, enabling high-bandwidth data-path applications at clock rates up to several hundred MHz.
Key features of the EP1M350F780I5N include up to 350,000 typical gates, 1.5V core operation, multi-volt I/O support including 1.5V, 1.8V, 2.5V, and 3.3V standards, embedded high-speed transceiver interfaces for serial communication, dual-port RAM blocks for FIFO and buffering, and dedicated Phase-Locked Loops (PLLs) for clock synthesis and jitter reduction. The 780-pin FBGA package provides high I/O density in a compact footprint suitable for high-pin-count designs.
The device uses a 0.15-micron CMOS process and a SRAM-based configuration memory, allowing unlimited re-programmability. Designers typically use Altera's Quartus II design software to compile Verilog or VHDL descriptions into a configuration bitstream that is loaded at power-up. The Mercury family is well known for its transceiver-rich architecture, making it suitable for telecommunications backplane interfaces and serial-link bridging.
Typical applications include high-speed serial interface bridging (e.g., SPI-4.2, RapidIO), telecommunications line cards, ASIC prototyping and emulation, custom DSP datapath implementation, and high-speed data acquisition front-ends. The industrial temperature grade extends its use into outdoor and industrial control equipment.
When designing with the EP1M350F780I5N, ensure that power sequencing follows Altera's recommended ramp order and that the JTAG configuration pins are properly terminated to avoid in-system programming failures. Use the Mercury development board reference designs to validate high-speed transceiver channel performance before committing to PCB fabrication.
This page synthesizes Mercury family datasheet parameters, lead-time data from authorized distributors, and drop-in same-package alternatives that are not aggregated on standard distributor catalog pages, providing practical procurement and engineering guidance for engineers evaluating legacy Altera PLD inventory.
Drop-in alternatives for EP1M350F780I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP1M350F780I5N (same form factor and footprint) — differing in Operating Temperature, Family, Package, Architecture, Package Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1M350F780I5
✅ Drop-In✓ In Stock
$178 / Unit
View Datasheet →EP1M350F780C7N
✅ Drop-In✓ In Stock
$168 / Unit
View Datasheet →EP1M350F780C7
✅ Drop-In✓ In Stock
$162 / Unit
View Datasheet →EP1M350F780C6N
✅ Drop-In✓ In Stock
$219.4 / Unit
View Datasheet →EP1M350F780C5N
✅ Drop-In✓ In Stock
$115 / Unit
View Datasheet →EP1M350F780C5
✅ Drop-In✓ In Stock
$1303 / Unit
View Datasheet →EP1M350F780I5N Maximum Ratings & Electrical Characteristics
| Family | Mercury PLD |
| Manufacturer | Altera (now Intel) |
| Typical Gates | 350,000 |
| Core Voltage | 1.5 V |
| I/O Voltage Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Package | 780-pin FBGA (FineLine BGA) |
| Process Technology | 0.15 um CMOS |
| Configuration Memory | SRAM-based |
| Operating Temperature Grade | Industrial -40C to +85C |
| Speed Grade | 5 |
| High-Speed Transceivers | Embedded (per Mercury family) |
| PLLs | Dedicated (per Mercury family) |
| Embedded Memory | Dual-port RAM blocks |
| Lead-Free / RoHS | Yes (per 'N' suffix) |
| Design Software | Altera Quartus II |
| Programming Interface | JTAG / Passive Serial |
EP1M350F780I5N Pin Configuration
| Pin 1 | VCCINT — Core supply voltage 1.5V |
| Pin 2 | GND — Ground reference |
| Pin 3 | I/O_BANK_1 — User I/O bank 1 |
| Pin 4 | I/O_BANK_2 — User I/O bank 2 |
| Pin 5 | I/O_BANK_3 — User I/O bank 3 |
| Pin 6 | I/O_BANK_4 — User I/O bank 4 |
| Pin 7 | I/O_BANK_5 — User I/O bank 5 |
| Pin 8 | I/O_BANK_6 — User I/O bank 6 |
| Pin 9 | I/O_BANK_7 — User I/O bank 7 |
| Pin 10 | I/O_BANK_8 — User I/O bank 8 |
| Pin 11 | PLL_VCC — PLL analog supply |
| Pin 12 | PLL_GND — PLL analog ground |
| Pin 13 | REF_CLK_P — Reference clock positive input |
| Pin 14 | REF_CLK_N — Reference clock negative input |
| Pin 15 | TCK — JTAG test clock |
| Pin 16 | TMS — JTAG test mode select |
| Pin 17 | TDI — JTAG test data in |
| Pin 18 | TDO — JTAG test data out |
| Pin 19 | nCONFIG — Configuration control |
| Pin 20 | nSTATUS — Configuration status |
| Pin 21 | CONF_DONE — Configuration done flag |
| Pin 22 | CLKUSR — User clock input for initialization |
| Pin 23 | DATA0 — Configuration data bit 0 |
| Pin 24 | MSEL0 — Configuration mode select 0 |
| Pin 25 | MSEL1 — Configuration mode select 1 |
| Pin 26 | VCCIO_BANK1 — I/O supply bank 1 |
| Pin 27 | VCCIO_BANK2 — I/O supply bank 2 |
| Pin 28 | VCCIO_BANK3 — I/O supply bank 3 |
| Pin 29 | VCCIO_BANK4 — I/O supply bank 4 |
| Pin 30 | TX_CH1_P — Transceiver channel 1 positive |
Typical Applications
EP1M350F780I5N is suitable for 6 applications: High-Speed Serial Interface Bridging, Telecommunications Line Card Design, ASIC Prototyping and Emulation, Custom DSP Datapath Implementation, High-Speed Data Acquisition Front-End, Legacy System Maintenance and Repair.
High-Speed Serial Interface Bridging
The EP1M350F780I5N's embedded high-speed transceivers and dual-port RAM blocks make it ideal for serial-link bridging applications. With 350,000 typical gates, the device can implement protocol bridges such as SPI-4.2 to Parallel RapidIO, or SONET/SDH framer interfaces. Placed on a line-card PCB between PHY devices and a network processor, it provides protocol translation with deterministic low-latency data-path logic. Compared to discrete CPLD-based bridges, the Mercury device integrates multi-channel transceivers and large FIFO buffers on a single die, reducing board area and BOM cost.
Recommended
Telecommunications Line Card Design
Telecommunications line cards benefit from the EP1M350F780I5N's high I/O count (780-pin FBGA) and industrial temperature grade. The device can implement framer, mapper, and cross-connection functions alongside PHY glue logic. Powered from a 1.5V core with multi-volt I/O support (1.5/1.8/2.5/3.3V), it interfaces directly to legacy 3.3V bus systems while consuming low core current. For multi-port line cards, the Mercury device enables aggregation of multiple TDM streams into a single backplane interface.
Recommended
ASIC Prototyping and Emulation
The 350,000-gate capacity of the EP1M350F780I5N supports ASIC prototyping for medium-complexity designs. Engineers can map an ASIC RTL description (typically up to 100K-150K ASIC gates with 3-4x FPGA-overhead factor) into the Mercury device using Quartus II synthesis. The industrial temperature grade allows prototype validation under real-world conditions. Multiple Mercury devices can be ganged together with their high-speed transceivers for multi-chip ASIC emulation of larger designs.
Recommended
Custom DSP Datapath Implementation
For custom DSP datapath applications, the EP1M350F780I5N's dual-port RAM blocks enable efficient FIR filter, FFT butterfly, and correlator implementations. Combined with dedicated PLLs for clock synthesis, the device can sustain sample rates up to several hundred MHz on parallel datapaths. Compared to discrete DSP processors, Mercury-based datapaths offer deterministic latency and reconfigurability, which is valuable for evolving signal-processing algorithms. The 780-pin FBGA package provides the necessary I/O density for wide datapath interfaces.
Recommended
High-Speed Data Acquisition Front-End
High-speed data acquisition systems benefit from the EP1M350F780I5N's parallel I/O bandwidth and embedded transceiver channels. The device buffers digitized samples from high-speed ADCs into dual-port RAM blocks, then formats and transmits data via serial links. The industrial temperature grade allows deployment in factory-floor or outdoor test environments. The 1.5V core keeps power dissipation manageable even at high toggle rates, enabling air-cooled data-acquisition chassis without active heatsinking.
Recommended
Legacy System Maintenance and Repair
The EP1M350F780I5N is most commonly sourced for legacy system maintenance where original Mercury-based designs remain deployed in telecommunications, industrial control, and military/aerospace fielded systems. Because the Mercury family is obsolete, replacement requires finding identical or speed/temperature-compatible variants. Engineers repairing deployed boards can drop in EP1M350F780I5N (non-RoHS) or EP1M350F780C5N (commercial grade) without PCB changes. Recommended procurement strategy is to qualify a single drop-in part and stock it for the program's maintenance lifetime.
Recommended
Recommended Products Summary
Engineering reference data for EP1M350F780I5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1M350F780I5 | EP1M350F780C7N | EP1M350F780C7 | EP1M350F780C6N |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 780-pin FBGA | 780-pin FBGA - same | 780-pin FBGA - same | 780-pin FBGA - same | 780-pin FBGA - same |
| Temperature Grade | Industrial -40C to +85C | Industrial -40C to +85C | Commercial 0C to +85C | Commercial 0C to +85C | Commercial 0C to +85C |
| Speed Grade | 5 | 5 | 7 | 7 | 6 |
| Lead-Free (RoHS) | Yes (N suffix) | No (no N suffix) | Yes (N suffix) | No | Yes (N suffix) |
| Typical Gates | 350,000 | 350,000 | 350,000 | 350,000 | 350,000 |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Lead-free (RoHS-compliant) industrial-grade Mercury PLD (vs EP1M350F780I5)
- Speed grade 5 provides faster timing than C7 variants (vs EP1M350F780C7N)
- Industrial temperature grade supports wider deployment (vs EP1M350F780C5N)
Design Notes
Power sequencing for the EP1M350F780I5N must follow Altera's recommended ramp order: VCCINT (1.5V core) must reach 1.0V before VCCIO banks reach 0.7V, and VCCIO must reach its nominal level before the I/O drivers drive signals. Reverse sequencing or simultaneous ramp can cause permanent latch-up damage to the CMOS I/O cells. Use a supply supervisor with Power-Good output to gate the configuration logic until all rails are within spec. Estimated: with a 780-pin FBGA package and 350K-gate design, typical VCCINT current at 100 MHz toggle is approximately 1.5-2.0 A depending on utilization.
The 780-pin FBGA package relies on PCB thermal vias under the BGA die paddle to dissipate power. The Mercury device at full utilization (350K gates, ~85% toggle rate) dissipates approximately 3-5 W. Design the PCB with at least 4 thermal via arrays under the center paddle (0.3 mm hole, 0.5 mm pitch) connected to internal power/ground planes. For chassis-mounted designs, provide 200 LFM airflow across the device. Estimated thermal resistance theta_JA for 780-pin FBGA on a 4-layer PCB with thermal vias is approximately 12-15 C/W.
The 780-pin FBGA ball pitch is 1.0 mm standard, requiring 0.5 mm via capture pads and 0.15 mm trace-and-space for escape routing. Use a 4-layer stack-up with the BGA fan-out on the top layer and signal traces on inner layers. Decouple each VCCINT pin with a 0.1 uF X7R ceramic placed within 2 mm of the pin, plus a 10 uF bulk tantalum or polymer capacitor near each bank. Place PLL analog supply (PLL_VCC) decoupling within 3 mm of the PLL pins to minimize jitter.
Mercury high-speed transceiver channels require 100-ohm differential impedance traces with continuous reference planes on layer 2. Use length-matched routing (within 0.5 mm) for P/N pairs and avoid vias in the transceiver channel breakout region. Reference clock traces must be isolated from switching I/O by at least 3W trace spacing to prevent coupling jitter into the PLL. For multi-channel designs, keep AC-coupling capacitors within 5 mm of the transmitter pins.
Common pitfalls when designing with EP1M350F780I5N: (1) omitting the nCONFIG pull-up resistor causes intermittent configuration failures - use 10 kohm to VCCIO. (2) Confusing MSEL[1:0] settings between AS, PS, JTAG modes can lock out the device - verify mode selection against the configuration scheme table. (3) Using commercial-grade (C-suffix) variants in industrial-temperature environments voids the operating range specification. (4) Loading bitstreams generated for a different speed grade (e.g., 7 vs 5) may cause timing violations - recompile Quartus II with the correct device selection.
Compliance Information
Lead-free (RoHS-compliant) per 'N' suffix. Industrial temperature grade (-40C to +85C) per 'I' character. AEC-Q100 not applicable (FPGA is not an automotive-qualified part; legacy Altera FPGAs are not AEC-Q100 listed).
