Intel

EP2SGX60EF1152C5N - Stratix II GX FPGA, 60K LE, 1152-FBGA | Intel

MPN: EP2SGX60EF1152C5N ⚠ Last Time Buy

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1.2 V Vdss 1152-ball FC-FBGA Package 609.76 MHz Speed 2,544,192 Memory

From $3300 USD / Unit

MOQ: 1 |

Price updated: 2026-09-08

Volume Pricing

Qty	Unit Price	Extended
1	$4250	$4,250.00
5	$4050	$20,250.00
10	$3825	$38,250.00
25	$3600	$90,000.00
100	$3300	$330,000.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EP2SGX60EF1152C5N Overview

The Intel EP2SGX60EF1152C5N is a high-density Stratix II GX Field Programmable Gate Array delivering 60,440 logic elements and 2,544,192 bits of embedded memory in a 1152-ball Flip-Chip FineLine BGA (FC-FBGA) package. It integrates 534 user I/Os and supports up to 609.76 MHz core operation on a 90 nm process with a 1.2 V core supply.

An FPGA (Field Programmable Gate Array) is a reconfigurable integrated circuit whose logic fabric, routing, and I/O cells are defined by a user-loaded configuration bitstream rather than hard-wired at the fab. Stratix II GX belongs to the FPGA -> programmable logic -> semiconductor hierarchy and was designed to combine high-density general-purpose logic with embedded transceivers for serial connectivity.

Key features include 3022 Logic Array Blocks (LABs), embedded 18x18 multipliers (typically 144 DSP blocks for the device family), high-speed serial transceivers supporting multi-gigabit rates, and Phase-Locked Loops (PLLs) for clock management. The FC-FBGA-1152 package uses flip-chip land-grid array construction that maximizes I/O density while minimizing electrical parasitics.

The 90 nm CMOS process with copper interconnect and 1.2 V core enables high toggle rates and aggressive integration, while the -5 speed grade denotes the mid-tier core performance bin. The Stratix II GX architecture pairs embedded transceivers with PCI Express hard IP blocks, supporting protocols such as PCI Express, Serial RapidIO, Gigabit Ethernet, and XAUI directly from the silicon.

Typical applications include high-speed serial interface bridges, ASIC prototyping, telecom line-card glue logic, military/aerospace signal processing, and broadcast video infrastructure. The -5 commercial speed grade is appropriate for laboratory and production designs where lower power and predictable timing closure are priorities.

Designers should plan for the 1152-ball FC-FBGA land pattern (35 mm or 40 mm body, depending on revision) and provide at least 6 PCB signal layers for break-out, plus dedicated ground/power planes for the 1.2 V core and 3.3 V/2.5 V/1.8 V I/O banks. Use the Quartus II design tool (or later Cyclone/Arria-compatible software where supported) for synthesis, place-and-route, and bitstream generation.

This page synthesizes distributor pricing, drop-in speed-grade and package alternatives, and practical design notes that supplement the manufacturer datasheet.

Drop-in alternatives for EP2SGX60EF1152C5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP2SGX60EF1152C5N (same form factor and footprint) — differing in Package, Speed Grade, Operating Temperature, Package Type, Mounting Type.

EP2SGX60E1152C

Intel

Package: 1152-ball FineLine BGA

Speed Grade: C (commercial, fastest)

Operating Temperature: 0C to +85C (commercial)