EP2A70F1508C9 - APEX II FPGA 67.2K LE 1.5V 1508-FBGA | Intel / Altera
MPN: EP2A70F1508C9 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1504.8 | $1,504.80 |
| 10 | $1475 | $14,750.00 |
| 50 | $1430 | $71,500.00 |
| 100 | $1380 | $138,000.00 |
| 500 | $1310 | $655,000.00 |
EP2A70F1508C9 Overview
A Field Programmable Gate Array (FPGA) is a semiconductor integrated circuit that lets engineers implement arbitrary digital logic, including complex state machines, datapaths, and signal-processing pipelines, after the device has been manufactured. Within the broader taxonomy, FPGAs sit inside the programmable logic family alongside CPLDs (Complex Programmable Logic Devices); programmable logic in turn belongs to the integrated-circuit / semiconductor hierarchy. FPGAs typically offer far higher logic density and more on-chip memory than CPLDs, at the cost of higher static power, longer configuration times, and more complex I/O signalling — and the APEX II family specifically extends density into the 30k–70k LE range with embedded CAM, embedded multipliers, and a range of fast I/O standards.
Key features of the EP2A70F1508C9 include 1,060 user I/O pins (per the 1508-BBGA FCBGA package), 4 PLLs, support for 1-Gbps True-LVDS, LVPECL, PCML, and HyperTransport™ interface signalling, dedicated carry and cascade chains for arithmetic-heavy designs, and on-chip memory that can be configured as RAM, ROM, or FIFO. Embedded Multipliers and CAM blocks accelerate DSP and lookup-table-style designs. Configuration can be loaded via passive serial, passive parallel synchronous/asynchronous, or via Altera's Fast Passive Parallel mode, and the device is supported by the Quartus II design toolchain (legacy Altera IDE).
Architecturally, the APEX II device combines a row/column-based LAB (Logic Array Block) structure with MultiTrack interconnect, embedded system blocks (ESBs) that provide true dual-port RAM, and dedicated clock networks. The C9 speed grade in the part number indicates a specific timing-bin; lower numbers generally mean faster FPGAs. Static current and I/O timing for the C9 grade are documented in the APEX II Device Family datasheet.
Typical applications include high-speed parallel interfaces, multi-gigabit serial backplanes, telecom line cards, test and measurement backplanes, DSP co-processing, and high-density glue logic. Designers also use APEX II devices for ASIC prototyping because of their high logic and memory capacity.
When designing with the EP2A70F1508C9, engineers must plan PCB layout for the 40 × 40 mm 1508-BGA footprint with 1 mm ball pitch, provide at least four PCB layers for power/ground and signal escape, and respect the I/O bank's VCCIO voltage rules (per I/O bank). Decoupling must follow the APEX II Hardware Reference manual recommendations, and signal-integrity analysis is recommended for any LVDS or LVPECL interface running at 1 Gbps. Engineers should also consider the device's NRND/EOL status before starting new designs.
Drop-in alternatives for EP2A70F1508C9 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2A70F1508C9 (same form factor and footprint) — differing in Package, Operating Temperature, Speed Grade, Series, Core Voltage.
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EP2A70F1508C8
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$1495 / Unit
View Datasheet →EP2A70F1508C8N
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View Datasheet →EP2A70F1508C8ES
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View Datasheet →EP2A70F1508C7
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View Datasheet →EP2A70F1508C7N
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View Datasheet →EP2A70F1508C6
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View Datasheet →EP2A70F1508C9 Maximum Ratings & Electrical Characteristics
| Series | APEX II |
| Family | APEX II FPGA |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements / Cells | 67,200 |
| Total RAM Bits | 1,146,880 |
| Number of I/O | 1,060 |
| Number of PLLs | 4 |
| Voltage - Supply (Core) | 1.425 V to 1.575 V |
| Mounting Type | Surface Mount |
| Package / Case | 1508-BBGA, FCBGA |
| Supplier Device Package | 1508-FBGA (40 × 40 mm) |
| Operating Temperature | 0 °C to 85 °C |
| Speed Grade | C9 |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers |
| High-Speed I/O Standards | True-LVDS (1 Gbps), LVPECL, PCML, HyperTransport |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, Fast Passive Parallel |
| Embedded Multiplier Blocks | Yes |
| Embedded Memory Type | Dual-port RAM (ESB) / ROM / FIFO |
EP2A70F1508C9 1508-fbga (40 × 40 mm) Pin Configuration Guide
Pin configuration for EP2A70F1508C9 (1508-fbga (40 × 40 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2A70F1508C9.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2A70F1508C9 is suitable for 6 applications: ASIC Prototyping, Telecom Line Cards, Test & Measurement Backplanes, DSP Co-Processing, High-Speed Serial Backplane Aggregation, Industrial Control & Glue Logic.
ASIC Prototyping
The EP2A70F1508C9 is a strong choice for ASIC prototyping because of its 67,200 logic elements and 1,060 user I/O pins in a single 1508-FBGA package. Designers can map mid-density ASICs (typically up to 1M ASIC gates) into the APEX II fabric, with the high I/O count enabling wide external bus bring-up, multiple memory interfaces, and clock-distribution replication. Quartus II supports both HDL synthesis and gate-level netlist import, so the same RTL that targets the final ASIC can be compiled for the APEX II. The trade-off versus a more modern Cyclone IV or Stratix prototype board is higher static power and legacy tooling, but pin-count and logic density remain competitive for sub-million-gate designs.
Recommended
Telecom Line Cards
The 1-Gbps True-LVDS, LVPECL, PCML, and HyperTransport™ support on the EP2A70F1508C9 makes it well-suited to telecom line cards that aggregate multiple E1/T1, E3, or 1-Gbps serial links. The device's 4 PLLs and dedicated I/O registers can deskew multi-channel LVDS traffic, and the 1,146,880 bits of embedded RAM buffer packet data at line rate. The 1508-FBGA package breaks out 1,060 user I/O pins, which is critical when the line card must connect to external framers, PHYs, and switch-fabric ASICs. For new designs the APEX II's last-time-buy status means telecom customers typically order life-time buy quantities up front.
Recommended
Test & Measurement Backplanes
The EP2A70F1508C9 fits test-and-measurement backplanes that need a programmable glue-logic and high-speed I/O hub. Its 1,060 user I/O pins let the FPGA aggregate dozens of mixed-signal front ends, while the 67,200 LEs implement on-chip state machines, pattern generators, and protocol decoders. APEX II's 1-Gbps LVDS capability supports connections to high-speed ADCs and DACs without external serializer/deserializer chips, reducing BOM. The 1,146,880-bit embedded RAM provides per-channel data buffers large enough to support deep capture memory, and the 4 PLLs let designers derive multiple precise sample clocks from a single reference.
Recommended
DSP Co-Processing
The EP2A70F1508C9 with 67,200 LEs and on-chip embedded multipliers can act as a DSP co-processor for baseband, video, or image processing. The APEX II family includes dedicated multiplier blocks plus a distributed MultiTrack interconnect, so common DSP kernels (FIR, FFT, correlation) achieve higher Fmax than in pure LUT-based FPGAs. The 1,146,880-bit embedded RAM provides dual-port coefficient and sample storage without external memory contention. Pairing this device with an external DSP or general-purpose processor allows a heterogeneous compute platform while keeping cost lower than high-end Stratix-class FPGAs.
Recommended
High-Speed Serial Backplane Aggregation
The EP2A70F1508C9 supports up to 1-Gbps LVDS, LVPECL, PCML, and HyperTransport™ signalling, which is ideal for backplanes aggregating multiple high-speed serial lanes. With 1,060 user I/O pins, the device can serve as a backplane bridge, merging many serial streams into a wider system bus or packet switch fabric. The on-chip PLLs and dedicated clock networks simplify multi-lane clocking, while the embedded RAM absorbs short bursts and rate-matching FIFOs. The 1508-FBGA package and 0–85 °C rating also suit controlled-environment central-office equipment.
Recommended
Industrial Control & Glue Logic
The EP2A70F1508C9 can replace banks of discrete glue logic, custom ASICs, and microcontrollers in industrial control systems. Its 67,200 LEs and 1,146,880 bits of embedded RAM provide the headroom to implement custom communication stacks (e.g., CAN, Modbus, Ethernet) alongside motion-control and machine-vision pipelines. The 1,060 user I/O pins make it easy to connect to sensors, motor drivers, and operator panels without external bus-expanders. Note that for true industrial temperature ranges, the I-grade variant EP2A70F1508I9 (−40 to 100 °C) should be used instead of the C9 commercial variant.
Recommended
Recommended Products Summary
Engineering reference data for EP2A70F1508C9 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2A70F1508C8 | EP2A70F1508C8N | EP2A70F1508C7 | EP2A70F1508C7N | EP2A70F1508C6 |
|---|---|---|---|---|---|---|
| Package | 1508-FBGA (40x40) | 1508-FBGA (40x40) - same | 1508-FBGA (40x40) - same | 1508-FBGA (40x40) - same | 1508-FBGA (40x40) - same | 1508-FBGA (40x40) - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Speed Grade | C9 (fastest) | C8 | C8 (lead-free) | C7 | C7 (lead-free) | C6 (slowest) |
| Logic Elements | 67,200 | 67,200 | 67,200 | 67,200 | ||
| Total RAM Bits | 1,146,880 | 1,146,880 | 1,146,880 | 1,146,880 | ||
| User I/O Pins | 1,060 | 1,060 | 1,060 | 1,060 | ||
| Core Voltage | 1.5 V (1.425–1.575 V) | 1.5 V | 1.5 V | 1.5 V | ||
| Operating Temperature | 0 °C to 85 °C (commercial) | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C |
Key Differentiators
- Fastest C9 speed grade in the APEX II 70-family (vs EP2A70F1508C8)
- Maximum I/O count and logic density in APEX II family (vs EP2A40F1508)
- Pin-compatible with the rest of the EP2A70F1508 family (vs EP2A70F1508C6)
Design Notes
The 1508-FBGA 1 mm-pitch package requires at least a 6-layer PCB stack-up with dedicated power and ground planes to escape the dense ball grid. BGA escape routing should follow the APEX II Hardware Reference manual ball-out map; a via-in-pad microvia process is recommended for fan-out, and via stubs must be back-drilled if the design uses >1 Gbps LVDS. Estimated: 1 mm pitch with 0.5 mm-diameter pads typically fits inside 4 signal layers plus 2 plane layers.
APEX II devices draw significant inrush current during configuration; decouple each VCCINT and VCCIO pin with a 0.1 µF ceramic cap placed as close to the ball as possible, plus bulk 100 µF tantalum or polymer caps at the regulator outputs. According to the APEX II datasheet, VCCINT tolerance is ±5 % (1.425 V–1.575 V), so use a low-dropout regulator with 1 % set-point accuracy and verify sequencing (VCCINT before VCCIO if the design mixes 3.3 V and 2.5 V I/O).
1-Gbps True-LVDS, LVPECL, and PCML interfaces on the EP2A70F1508C9 require controlled-impedance routing (100 Ω differential) with matched lengths within the skew tolerance reported in the device handbook. Pair-to-pair length matching of <50 ps is recommended; this typically translates to <5 mm length match on FR-4 with 150 ps/in propagation delay. Use a HyperLynx or Siwave pre-layout simulation to verify channel loss at 1 Gbps.
Because the APEX II family is in last-time-buy, do not design new production boards with the EP2A70F1508C9 unless you can secure a life-time buy. Common pitfalls include using the wrong MSL (Moisture Sensitivity Level) for reflow profile — BGA packages typically require MSL3 dry-bag handling — and assuming newer Quartus versions support APEX II (only Quartus II 9.x / 10.x do, so budget for legacy toolchain maintenance).
Differential I/O pairs on the APEX II share a dedicated PLL clock network; group high-speed serial pairs adjacent to their PLL clock pin to minimize clock skew, and use the Quartus Pin Planner to lock I/O assignments before PCB layout. Keep at least 2 mm clearance between LVDS pairs and any single-ended LVCMOS signals to avoid coupled noise, and stitch the BGA ground balls with at least four stitched vias per quadrant for low-impedance return paths.
Compliance Information
RoHS / REACH / halogen status was not present in the verified web data; lead-free per Altera/Intel legacy APEX II product page. AEC-Q100 not applicable — APEX II is not an automotive-grade FPGA family. For new automotive designs consider Cyclone IV E/GX AEC-Q100 variants.
